// If the 2nd shift is bigger than the 1st, we can fold:
// shr(c1) + shl(c2) -> shl(c3) + and(c4)
// but it isn't profitable unless we know the and'd out bits are already zero.
- if (SecondShiftAmt > FirstShiftAmt) {
+ // Also check that the 2nd shift is valid (less than the type width) or we'll
+ // crash trying to produce the bit mask for the 'and'.
+ if (SecondShiftAmt > FirstShiftAmt && SecondShiftAmt < TypeWidth) {
unsigned MaskShift = TypeWidth - SecondShiftAmt;
APInt Mask = APInt::getLowBitsSet(TypeWidth, FirstShiftAmt) << MaskShift;
if (IC.MaskedValueIsZero(SecondShift->getOperand(0), Mask, 0, CxtI))
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -instcombine -S | FileCheck %s
-; This would crash if we didn't check for a negative shift.
+; These would crash if we didn't check for a negative shift.
+
+; https://llvm.org/bugs/show_bug.cgi?id=12967
define void @pr12967() {
; CHECK-LABEL: @pr12967(
br label %loop
}
+; https://llvm.org/bugs/show_bug.cgi?id=26760
+
+define void @pr26760() {
+; CHECK-LABEL: @pr26760(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label %loop
+; CHECK: loop:
+; CHECK-NEXT: br label %loop
+;
+entry:
+ br label %loop
+
+loop:
+ %c = phi i32 [ %shl, %loop ], [ undef, %entry ]
+ %shr = lshr i32 %c, 7
+ %shl = shl i32 %shr, -2
+ br label %loop
+}
+