break;
case SN_Divide:
case SN_op_Division:
+ if (strcmp ("Vector4", m_class_get_name (klass)) && strcmp ("Vector2", m_class_get_name (klass))) {
+ if ((fsig->params [0]->type == MONO_TYPE_GENERICINST) && (fsig->params [1]->type != MONO_TYPE_GENERICINST)) {
+ MonoInst* ins = emit_simd_ins (cfg, klass, OP_CREATE_SCALAR_UNSAFE, args [1]->dreg, -1);
+ ins->inst_c1 = arg_type;
+ ins = emit_simd_ins (cfg, klass, OP_XBINOP_BYSCALAR, args [0]->dreg, ins->dreg);
+ ins->inst_c0 = OP_FDIV;
+ return ins;
+ } else if ((fsig->params [0]->type == MONO_TYPE_GENERICINST) && (fsig->params [1]->type == MONO_TYPE_GENERICINST)) {
+ instc0 = OP_FDIV;
+ break;
+ } else {
+ return NULL;
+ }
+ }
instc0 = OP_FDIV;
break;
case SN_Max:
ins = emit_simd_ins (cfg, klass, OP_XBINOP_BYSCALAR, ins->dreg, args [1]->dreg);
ins->inst_c0 = OP_FMUL;
return ins;
+ } else if ((fsig->params [0]->type == MONO_TYPE_GENERICINST) && (fsig->params [1]->type == MONO_TYPE_GENERICINST)) {
+ instc0 = OP_FMUL;
+ break;
+ } else {
+ return NULL;
}
}
instc0 = OP_FMUL;