[X86] Remove unnecessary overrides for CBW/CWDE/CDQE/CMC instructions

All of these match the default WriteALU schedule

diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 5f47a7d..2cc479b 100644 (file)
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -957,8 +957,7 @@ def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[HWWriteResGroup10], (instrs CBW, CWDE, CDQE,
-                                         CMC, STC,
+def: InstRW<[HWWriteResGroup10], (instrs STC,
                                          SGDT64m,
                                          SIDT64m,
                                          SMSW16m,

diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td
index d6ca00f..ce9e254 100644 (file)
--- a/llvm/lib/Target/X86/X86SchedIceLake.td
+++ b/llvm/lib/Target/X86/X86SchedIceLake.td
@@ -727,8 +727,7 @@ def ICXWriteResGroup10 : SchedWriteRes<[ICXPort0156]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[ICXWriteResGroup10], (instrs CBW, CWDE, CDQE,
-                                          CMC, STC,
+def: InstRW<[ICXWriteResGroup10], (instrs STC,
                                           SGDT64m,
                                           SIDT64m,
                                           SMSW16m,

diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index a054fb0..e6d7a46 100644 (file)
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -689,8 +689,7 @@ def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE,
-                                          CMC, STC,
+def: InstRW<[SKLWriteResGroup10], (instrs STC,
                                           SGDT64m,
                                           SIDT64m,
                                           SMSW16m,

diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index 9343423..c4b5ebe 100644 (file)
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -709,8 +709,7 @@ def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE,
-                                          CMC, STC,
+def: InstRW<[SKXWriteResGroup10], (instrs STC,
                                           SGDT64m,
                                           SIDT64m,
                                           SMSW16m,