usb/penwell_otg: extend ulpi access timeout value

BZ: 26396

This patch extends the ulpi access timeout to 2ms, as we found sometime
the ulpi access response is slow and cause unexpected timeout event.
The unexpected timeout event will cause USB HW/SW stack reset and make
some compliance test failed due to reset.

Change-Id: I03a54e9f8329ae116d81f18954130b9da64847f2
Signed-off-by: Wu, Hao <hao.wu@intel.com>
Reviewed-on: http://android.intel.com:8080/37985
Reviewed-by: Li, Wenji <wenji.li@intel.com>
Reviewed-by: Zhuang, Jin Can <jin.can.zhuang@intel.com>
Reviewed-by: Tang, Richard <richard.tang@intel.com>
Reviewed-by: Meng, Zhe <zhe.meng@intel.com>
Tested-by: Meng, Zhe <zhe.meng@intel.com>
Reviewed-by: buildbot <buildbot@intel.com>
Tested-by: buildbot <buildbot@intel.com>

diff --git a/drivers/usb/otg/penwell_otg.c b/drivers/usb/otg/penwell_otg.c
index 2b97c8f..5885b31 100644 (file)
--- a/drivers/usb/otg/penwell_otg.c
+++ b/drivers/usb/otg/penwell_otg.c
@@ -665,8 +665,8 @@ penwell_otg_ulpi_read(struct intel_mid_otg_xceiv *iotg, u8 reg, u8 *val)
        val32 = ULPI_RUN | reg << 16;
        writel(val32, pnw->iotg.base + CI_ULPIVP);
 
-       /* Polling at least 1ms for read operation to complete*/
-       count = 200;
+       /* Polling at least 2ms for read operation to complete*/
+       count = 400;
 
        while (count) {
                val32 = readl(pnw->iotg.base + CI_ULPIVP);
@@ -701,8 +701,8 @@ penwell_otg_ulpi_write(struct intel_mid_otg_xceiv *iotg, u8 reg, u8 val)
        val32 = ULPI_RUN | ULPI_RW | reg << 16 | val;
        writel(val32, pnw->iotg.base + CI_ULPIVP);
 
-       /* Polling at least 1ms for write operation to complete*/
-       count = 200;
+       /* Polling at least 2ms for write operation to complete*/
+       count = 400;
 
        while (count && penwell_otg_ulpi_run()) {
                count--;