freedreno/a5xx: set SP_BLEND_CONTROL properly
authorRob Clark <robdclark@gmail.com>
Tue, 6 Jun 2017 17:15:02 +0000 (13:15 -0400)
committerRob Clark <robdclark@gmail.com>
Wed, 7 Jun 2017 16:32:00 +0000 (12:32 -0400)
Signed-off-by: Rob Clark <robdclark@gmail.com>
src/gallium/drivers/freedreno/a5xx/fd5_blend.c
src/gallium/drivers/freedreno/a5xx/fd5_blend.h
src/gallium/drivers/freedreno/a5xx/fd5_emit.c

index 42918f7..25d9946 100644 (file)
@@ -142,6 +142,8 @@ fd5_blend_state_create(struct pipe_context *pctx,
 
        so->rb_blend_cntl = A5XX_RB_BLEND_CNTL_ENABLE_BLEND(mrt_blend) |
                COND(cso->independent_blend_enable, A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND);
+       so->sp_blend_cntl = A5XX_SP_BLEND_CNTL_UNK8 |
+               COND(mrt_blend, A5XX_SP_BLEND_CNTL_ENABLED);
 
        return so;
 }
index f758738..6985495 100644 (file)
@@ -46,6 +46,7 @@ struct fd5_blend_stateobj {
                uint32_t blend_control_alpha;
        } rb_mrt[A5XX_MAX_RENDER_TARGETS];
        uint32_t rb_blend_cntl;
+       uint32_t sp_blend_cntl;
        bool lrz_write;
 };
 
index 0f65802..f5c0bd2 100644 (file)
@@ -694,7 +694,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
                                A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
 
                OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
-               OUT_RING(ring, 0x00000100);
+               OUT_RING(ring, blend->sp_blend_cntl);
        }
 
        if (dirty & FD_DIRTY_BLEND_COLOR) {