drm/amdgpu/: add more macro to support offset variant

Add more macro to support offset variant and
simplify macro SOC15_WAIT_ON_RREG.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a277bdc..00c52ca 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1082,6 +1082,9 @@ size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
 
 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
                               void *buf, size_t size, bool write);
+uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
+                           uint32_t inst, uint32_t reg_addr, char reg_name[],
+                           uint32_t expected_value, uint32_t mask);
 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
                            uint32_t reg, uint32_t acc_flags);
 void amdgpu_device_wreg(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f432064..82a3d0f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -6081,3 +6081,31 @@ bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
                return true;
        }
 }
+
+uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
+               uint32_t inst, uint32_t reg_addr, char reg_name[],
+               uint32_t expected_value, uint32_t mask)
+{
+       uint32_t ret = 0;
+       uint32_t old_ = 0;
+       uint32_t tmp_ = RREG32(reg_addr);
+       uint32_t loop = adev->usec_timeout;
+
+       while ((tmp_ & (mask)) != (expected_value)) {
+               if (old_ != tmp_) {
+                       loop = adev->usec_timeout;
+                       old_ = tmp_;
+               } else
+                       udelay(1);
+               tmp_ = RREG32(reg_addr);
+               loop--;
+               if (!loop) {
+                       DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn",
+                                 inst, reg_name, (uint32_t)expected_value,
+                                 (uint32_t)(tmp_ & (mask)));
+                       ret = -ETIMEDOUT;
+                       break;
+               }
+       }
+       return ret;
+}

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index 3f6dac8..eb35096 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -26,6 +26,8 @@
 
 /* Register Access Macros */
 #define SOC15_REG_OFFSET(ip, inst, reg)        (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
+#define SOC15_REG_OFFSET1(ip, inst, reg, offset) \
+       (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset))
 
 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
        ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
@@ -86,31 +88,15 @@
         __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
                          value, 0, ip##_HWIP)
 
-#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
-({     int ret = 0;                                            \
-       do {                                                    \
-               uint32_t old_ = 0;                              \
-               uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
-               uint32_t loop = adev->usec_timeout;             \
-               ret = 0;                                        \
-               while ((tmp_ & (mask)) != (expected_value)) {   \
-                       if (old_ != tmp_) {                     \
-                               loop = adev->usec_timeout;      \
-                               old_ = tmp_;                    \
-                       } else                                  \
-                               udelay(1);                      \
-                       tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
-                       loop--;                                 \
-                       if (!loop) {                            \
-                               DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \
-                                         inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \
-                               ret = -ETIMEDOUT;               \
-                               break;                          \
-                       }                                       \
-               }                                               \
-       } while (0);                                            \
-       ret;                                                    \
-})
+#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask)      \
+       amdgpu_device_wait_on_rreg(adev, inst,                       \
+       (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)), \
+       #reg, expected_value, mask)
+
+#define SOC15_WAIT_ON_RREG_OFFSET(ip, inst, reg, offset, expected_value, mask)  \
+       amdgpu_device_wait_on_rreg(adev, inst,                                  \
+       (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg) + (offset)), \
+       #reg, expected_value, mask)
 
 #define WREG32_RLC(reg, value) \
        __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)