LiveIntervals: Split live intervals on multiple dead defs

If there are multiple dead defs of the same virtual register, these
are required to be split into multiple virtual registers with separate
live intervals to avoid a verifier error.

llvm-svn: 371640

diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index 0781a0b..2d5b8e7 100644 (file)
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -196,7 +196,11 @@ void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
   assert(LI.empty() && "Should only compute empty intervals.");
   LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
   LRCalc->calculate(LI, MRI->shouldTrackSubRegLiveness(LI.reg));
-  computeDeadValues(LI, nullptr);
+
+  if (computeDeadValues(LI, nullptr)) {
+    SmallVector<LiveInterval *, 4> SplitIntervals;
+    splitSeparateComponents(LI, SplitIntervals);
+  }
 }
 
 void LiveIntervals::computeVirtRegs() {
@@ -500,6 +504,8 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li,
 bool LiveIntervals::computeDeadValues(LiveInterval &LI,
                                       SmallVectorImpl<MachineInstr*> *dead) {
   bool MayHaveSplitComponents = false;
+  bool HaveDeadDef = false;
+
   for (VNInfo *VNI : LI.valnos) {
     if (VNI->isUnused())
       continue;
@@ -530,6 +536,10 @@ bool LiveIntervals::computeDeadValues(LiveInterval &LI,
       MachineInstr *MI = getInstructionFromIndex(Def);
       assert(MI && "No instruction defining live value");
       MI->addRegisterDead(LI.reg, TRI);
+      if (HaveDeadDef)
+        MayHaveSplitComponents = true;
+      HaveDeadDef = true;
+
       if (dead && MI->allDefsAreDead()) {
         LLVM_DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
         dead->push_back(MI);

diff --git a/llvm/test/CodeGen/AMDGPU/live-intervals-multiple-dead-defs.mir b/llvm/test/CodeGen/AMDGPU/live-intervals-multiple-dead-defs.mir
new file mode 100644 (file)
index 0000000..4c402d7
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/live-intervals-multiple-dead-defs.mir
@@ -0,0 +1,18 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
+
+# There are multiple dead defs of the same virtual register. Make sure
+# the intervals are split during the initial live range computation.
+
+---
+name:            multiple_connected_components_dead
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK-LABEL: name: multiple_connected_components_dead
+    ; CHECK: dead %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; CHECK: dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    dead %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    dead %0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+
+...