[MIPS GlobalISel] Select sqrt

Select G_FSQRT for MIPS32.

Differential Revision: https://reviews.llvm.org/D62905

llvm-svn: 362692

diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index 9161a0f..c48b6da 100644 (file)
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -94,7 +94,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
   getActionDefinitionsBuilder(G_FCONSTANT)
       .legalFor({s32, s64});
 
-  getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS})
+  getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT})
       .legalFor({s32, s64});
 
   getActionDefinitionsBuilder(G_FCMP)

diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
index 3ac81f7..9adc1b9 100644 (file)
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -134,7 +134,8 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case G_FSUB:
   case G_FMUL:
   case G_FDIV:
-  case G_FABS: {
+  case G_FABS:
+  case G_FSQRT:{
     unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
     assert((Size == 32 || Size == 64) && "Unsupported floating point size");
     OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]

diff --git a/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt.mir b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt.mir
new file mode 100644 (file)
index 0000000..a77f287
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/fsqrt.mir
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+  define void @sqrt_f32() {entry: ret void}
+  define void @sqrt_f64() {entry: ret void}
+
+...
+---
+name:            sqrt_f32
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $f12
+
+    ; FP32-LABEL: name: sqrt_f32
+    ; FP32: liveins: $f12
+    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+    ; FP32: [[FSQRT_S:%[0-9]+]]:fgr32 = FSQRT_S [[COPY]]
+    ; FP32: $f0 = COPY [[FSQRT_S]]
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: sqrt_f32
+    ; FP64: liveins: $f12
+    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+    ; FP64: [[FSQRT_S:%[0-9]+]]:fgr32 = FSQRT_S [[COPY]]
+    ; FP64: $f0 = COPY [[FSQRT_S]]
+    ; FP64: RetRA implicit $f0
+    %0:fprb(s32) = COPY $f12
+    %1:fprb(s32) = G_FSQRT %0
+    $f0 = COPY %1(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            sqrt_f64
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $d6
+
+    ; FP32-LABEL: name: sqrt_f64
+    ; FP32: liveins: $d6
+    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
+    ; FP32: [[FSQRT_D32_:%[0-9]+]]:afgr64 = FSQRT_D32 [[COPY]]
+    ; FP32: $d0 = COPY [[FSQRT_D32_]]
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: sqrt_f64
+    ; FP64: liveins: $d6
+    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
+    ; FP64: [[FSQRT_D64_:%[0-9]+]]:fgr64 = FSQRT_D64 [[COPY]]
+    ; FP64: $d0 = COPY [[FSQRT_D64_]]
+    ; FP64: RetRA implicit $d0
+    %0:fprb(s64) = COPY $d6
+    %1:fprb(s64) = G_FSQRT %0
+    $d0 = COPY %1(s64)
+    RetRA implicit $d0
+
+...

diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt.mir
new file mode 100644 (file)
index 0000000..186498a
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fsqrt.mir
@@ -0,0 +1,61 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+  define void @sqrt_f32() {entry: ret void}
+  define void @sqrt_f64() {entry: ret void}
+
+...
+---
+name:            sqrt_f32
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $f12
+
+    ; FP32-LABEL: name: sqrt_f32
+    ; FP32: liveins: $f12
+    ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+    ; FP32: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]]
+    ; FP32: $f0 = COPY [[FSQRT]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: sqrt_f32
+    ; FP64: liveins: $f12
+    ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+    ; FP64: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]]
+    ; FP64: $f0 = COPY [[FSQRT]](s32)
+    ; FP64: RetRA implicit $f0
+    %0:_(s32) = COPY $f12
+    %1:_(s32) = G_FSQRT %0
+    $f0 = COPY %1(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            sqrt_f64
+alignment:       2
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $d6
+
+    ; FP32-LABEL: name: sqrt_f64
+    ; FP32: liveins: $d6
+    ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+    ; FP32: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]]
+    ; FP32: $d0 = COPY [[FSQRT]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: sqrt_f64
+    ; FP64: liveins: $d6
+    ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+    ; FP64: [[FSQRT:%[0-9]+]]:_(s64) = G_FSQRT [[COPY]]
+    ; FP64: $d0 = COPY [[FSQRT]](s64)
+    ; FP64: RetRA implicit $d0
+    %0:_(s64) = COPY $d6
+    %1:_(s64) = G_FSQRT %0
+    $d0 = COPY %1(s64)
+    RetRA implicit $d0
+
+...

diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll
new file mode 100644 (file)
index 0000000..1bca4e8
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+
+declare float @llvm.sqrt.f32(float)
+define float @sqrt_f32(float %a) {
+; MIPS32-LABEL: sqrt_f32:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sqrt.s $f0, $f12
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = call float @llvm.sqrt.f32(float %a)
+  ret float %0
+}
+
+declare double @llvm.sqrt.f64(double)
+define double @sqrt_f64(double %a) {
+; MIPS32-LABEL: sqrt_f64:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sqrt.d $f0, $f12
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %0 = call double @llvm.sqrt.f64(double %a)
+  ret double %0
+}

diff --git a/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir
new file mode 100644 (file)
index 0000000..ba86c15
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/fsqrt.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+  define void @sqrt_f32() {entry: ret void}
+  define void @sqrt_f64() {entry: ret void}
+
+...
+---
+name:            sqrt_f32
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $f12
+
+    ; FP32-LABEL: name: sqrt_f32
+    ; FP32: liveins: $f12
+    ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+    ; FP32: [[FSQRT:%[0-9]+]]:fprb(s32) = G_FSQRT [[COPY]]
+    ; FP32: $f0 = COPY [[FSQRT]](s32)
+    ; FP32: RetRA implicit $f0
+    ; FP64-LABEL: name: sqrt_f32
+    ; FP64: liveins: $f12
+    ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+    ; FP64: [[FSQRT:%[0-9]+]]:fprb(s32) = G_FSQRT [[COPY]]
+    ; FP64: $f0 = COPY [[FSQRT]](s32)
+    ; FP64: RetRA implicit $f0
+    %0:_(s32) = COPY $f12
+    %1:_(s32) = G_FSQRT %0
+    $f0 = COPY %1(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            sqrt_f64
+alignment:       2
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $d6
+
+    ; FP32-LABEL: name: sqrt_f64
+    ; FP32: liveins: $d6
+    ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+    ; FP32: [[FSQRT:%[0-9]+]]:fprb(s64) = G_FSQRT [[COPY]]
+    ; FP32: $d0 = COPY [[FSQRT]](s64)
+    ; FP32: RetRA implicit $d0
+    ; FP64-LABEL: name: sqrt_f64
+    ; FP64: liveins: $d6
+    ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+    ; FP64: [[FSQRT:%[0-9]+]]:fprb(s64) = G_FSQRT [[COPY]]
+    ; FP64: $d0 = COPY [[FSQRT]](s64)
+    ; FP64: RetRA implicit $d0
+    %0:_(s64) = COPY $d6
+    %1:_(s64) = G_FSQRT %0
+    $d0 = COPY %1(s64)
+    RetRA implicit $d0
+
+...