2009-02-04 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (January, 2009)
* config/i386/sse.md (*vpclmulqdq): New.
gcc/testsuite/
2009-02-04 H.J. Lu <hongjiu.lu@intel.com>
AVX Programming Reference (January, 2009)
* gcc.target/i386/avx-vpclmulqdq.c: New.
* gcc.target/i386/pclmul-avx-check.h: Likewise.
* gcc.target/i386/i386.exp (check_effective_target_vpclmul): New.
* gcc.target/i386/pclmulqdq.c (CHECK_H): New.
(TEST): Likewise.
Include CHECK_H instead of "pclmul-check.h".
(pclmul_test): Renamed to ...
(TEST): This.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@143938
138bc75d-0d04-0410-961f-
82ee72b054a4
+2009-02-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ AVX Programming Reference (January, 2009)
+ * config/i386/sse.md (*vpclmulqdq): New.
+
2009-02-04 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/38977
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
+(define_insn "*vpclmulqdq"
+ [(set (match_operand:V2DI 0 "register_operand" "=x")
+ (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
+ (match_operand:V2DI 2 "nonimmediate_operand" "xm")
+ (match_operand:SI 3 "const_0_to_255_operand" "n")]
+ UNSPEC_PCLMUL))]
+ "TARGET_PCLMUL && TARGET_AVX"
+ "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+ [(set_attr "type" "sselog1")
+ (set_attr "prefix" "vex")
+ (set_attr "mode" "TI")])
+
(define_insn "pclmulqdq"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
+2009-02-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ AVX Programming Reference (January, 2009)
+ * gcc.target/i386/avx-vpclmulqdq.c: New.
+ * gcc.target/i386/pclmul-avx-check.h: Likewise.
+
+ * gcc.target/i386/i386.exp (check_effective_target_vpclmul): New.
+
+ * gcc.target/i386/pclmulqdq.c (CHECK_H): New.
+ (TEST): Likewise.
+ Include CHECK_H instead of "pclmul-check.h".
+ (pclmul_test): Renamed to ...
+ (TEST): This.
+
2009-02-04 Jakub Jelinek <jakub@redhat.com>
PR c++/39095
--- /dev/null
+/* { dg-do run } */
+/* { dg-require-effective-target vpclmul } */
+/* { dg-options "-O2 -mpclmul -mavx" } */
+
+#define CHECK_H "pclmul-avx-check.h"
+#define TEST pclmul_avx_test
+
+#include "pclmulqdq.c"
} "-O2 -mpclmul" ]
}
+# Return 1 if vpclmul instructions can be compiled.
+proc check_effective_target_vpclmul { } {
+ return [check_no_compiler_messages vpclmul object {
+ typedef long long __m128i __attribute__ ((__vector_size__ (16)));
+ typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+
+ __m128i pclmulqdq_test (__m128i __X, __m128i __Y)
+ {
+ return (__m128i) __builtin_ia32_pclmulqdq128 ((__v2di)__X,
+ (__v2di)__Y,
+ 1);
+ }
+ } "-O2 -mpclmul -mavx" ]
+}
+
# Return 1 if sse4a instructions can be compiled.
proc check_effective_target_sse4a { } {
return [check_no_compiler_messages sse4a object {
--- /dev/null
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+#include <stdlib.h>
+#include "cpuid.h"
+
+static void pclmul_avx_test (void);
+
+int
+main ()
+{
+ unsigned int eax, ebx, ecx, edx;
+
+ if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
+ return 0;
+
+ /* Run PCLMUL + AVX test only if host has PCLMUL + AVX support. */
+ if ((ecx & (bit_AVX | bit_PCLMUL)) == (bit_AVX | bit_PCLMUL))
+ {
+ pclmul_avx_test ();
+#ifdef DEBUG
+ printf ("PASSED\n");
+#endif
+ }
+#ifdef DEBUG
+ else
+ printf ("SKIPPED\n");
+#endif
+
+ return 0;
+}
/* { dg-require-effective-target pclmul } */
/* { dg-options "-O2 -mpclmul" } */
+#ifndef CHECK_H
+#define CHECK_H "pclmul-check.h"
+#endif
+
+#ifndef TEST
+#define TEST pclmul_test
+#endif
+
+#include CHECK_H
+
#include <wmmintrin.h>
#include <string.h>
-#include "pclmul-check.h"
-
extern void abort (void);
#define NUM 1024
}
static void
-pclmul_test (void)
+TEST (void)
{
int i;