#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
puts("Work-around for Erratum CPU22 enabled\n");
#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
+ puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
+#endif
return 0;
}
{
phys_size_t dram_size = 0;
-#if defined(CONFIG_DDR_DLL)
+#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
unsigned int x = 10;
also manual config the DDR after undef this
definition.
CONFIG_DDR_ECC only for ECC DDR module
- CONFIG_DDR_DLL DLL fix on some ADS boards needed for more
- stability.
+ CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN DLL fix on some ADS boards needed
+ for more stability.
CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0.
Other than the above definitions, the rest in the config files are
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
-#undef CONFIG_DDR_DLL
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
-#define CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
-#undef CONFIG_DDR_DLL
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#undef CONFIG_DDR_DLL
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#undef CONFIG_DDR_SPD
#if defined(CONFIG_MPC85xx_REV1)
- #define CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#endif
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
/* TQM8540 & 8560 need DLL-override */
-#define CONFIG_DDR_DLL /* DLL fix needed */
+#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
#undef CONFIG_DDR_SPD
#if defined(CONFIG_MPC85xx_REV1)
- #define CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#endif
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef