As PR103627 shows, there is an unexpected case where !TARGET_VSX
and TARGET_MMA co-exist. As ISA3.1 claims, SIMD is a requirement
for MMA. By looking into the ICE, I noticed that the current
MMA implementation depends on vector pairs load/store which use
VSX register, but we don't have a separated option to control
Power10 vector support and Segher pointed out "-mpower9-vector is
a workaround that should go away" and more explanations in [1].
So this patch makes MMA require VSX instead.
[1] https://gcc.gnu.org/pipermail/gcc-patches/2022-January/589303.html
gcc/ChangeLog:
PR target/103627
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Disable
MMA if !TARGET_VSX.
gcc/testsuite/ChangeLog:
PR target/103627
* gcc.target/powerpc/pr103627-1.c: New test.
* gcc.target/powerpc/pr103627-2.c: New test.
rs6000_isa_flags &= ~OPTION_MASK_MMA;
}
+ /* MMA requires SIMD support as ISA 3.1 claims and our implementation
+ such as "*movoo" uses vector pair access which use VSX registers.
+ So make MMA require VSX support here. */
+ if (TARGET_MMA && !TARGET_VSX)
+ {
+ if ((rs6000_isa_flags_explicit & OPTION_MASK_MMA) != 0)
+ error ("%qs requires %qs", "-mmma", "-mvsx");
+ rs6000_isa_flags &= ~OPTION_MASK_MMA;
+ }
+
if (!TARGET_PCREL && TARGET_PCREL_OPT)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
--- /dev/null
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -mno-vsx" } */
+
+/* Verify compiler emits error message instead of ICE. */
+
+extern float *dest;
+extern __vector_quad src;
+
+int
+foo ()
+{
+ __builtin_mma_disassemble_acc (dest, &src);
+ /* { dg-error "'__builtin_mma_disassemble_acc' requires the '-mmma' option" "" { target *-*-* } .-1 } */
+ return 0;
+}
+
--- /dev/null
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -mmma -mno-vsx" } */
+
+/* Verify the emitted error message. */
+
+extern float *dest;
+extern __vector_quad src;
+
+int
+foo ()
+{
+ __builtin_mma_disassemble_acc (dest, &src);
+ /* { dg-error "'-mmma' requires '-mvsx'" "mma" { target *-*-* } 0 } */
+ return 0;
+}
+