#define AMDGPU_SIENNA_CICHLID_RANGE 0x28, 0x32
#define AMDGPU_NAVY_FLOUNDER_RANGE 0x32, 0x3C
#define AMDGPU_DIMGREY_CAVEFISH_RANGE 0x3C, 0x46
+#define AMDGPU_BEIGE_GOBY_RANGE 0x46, 0x50
#define AMDGPU_VANGOGH_RANGE 0x01, 0xFF
#define ASICREV_IS_SIENNA_CICHLID(r) ASICREV_IS(r, SIENNA_CICHLID)
#define ASICREV_IS_NAVY_FLOUNDER(r) ASICREV_IS(r, NAVY_FLOUNDER)
#define ASICREV_IS_DIMGREY_CAVEFISH(r) ASICREV_IS(r, DIMGREY_CAVEFISH)
+#define ASICREV_IS_BEIGE_GOBY(r) ASICREV_IS(r, BEIGE_GOBY)
#define ASICREV_IS_VANGOGH(r) ASICREV_IS(r, VANGOGH)
m_settings.supportRbPlus = 1;
m_settings.dccUnsup3DSwDis = 0;
}
+
+ if (ASICREV_IS_BEIGE_GOBY(chipRevision))
+ {
+ m_settings.supportRbPlus = 1;
+ m_settings.dccUnsup3DSwDis = 0;
+ }
break;
case FAMILY_VGH:
identify_chip(SIENNA_CICHLID);
identify_chip(NAVY_FLOUNDER);
identify_chip(DIMGREY_CAVEFISH);
+ identify_chip(BEIGE_GOBY);
break;
case FAMILY_VGH:
identify_chip(VANGOGH);
pc_lines = 1024;
break;
case CHIP_NAVI14:
+ case CHIP_BEIGE_GOBY:
pc_lines = 512;
break;
case CHIP_VANGOGH:
return "dimgrey_cavefish";
case CHIP_VANGOGH:
return "vangogh";
+ case CHIP_BEIGE_GOBY:
+ return "beige_goby";
case CHIP_YELLOW_CARP:
return "yellow_carp";
default:
CHIP_NAVY_FLOUNDER,
CHIP_VANGOGH,
CHIP_DIMGREY_CAVEFISH,
+ CHIP_BEIGE_GOBY,
CHIP_YELLOW_CARP,
CHIP_LAST,
};
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
+ case CHIP_BEIGE_GOBY:
case CHIP_VANGOGH:
case CHIP_YELLOW_CARP:
return "gfx1030";
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
+ case CHIP_BEIGE_GOBY:
case CHIP_VANGOGH:
case CHIP_YELLOW_CARP:
dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
switch (param) {
case PIPE_VIDEO_CAP_SUPPORTED:
if (codec < PIPE_VIDEO_FORMAT_MPEG4_AVC &&
- sscreen->info.family >= CHIP_YELLOW_CARP)
+ sscreen->info.family >= CHIP_BEIGE_GOBY)
return false;
switch (codec) {
case PIPE_VIDEO_FORMAT_MPEG12: