drm/amdgpu: Optimize amdgpu_nbio_ras_late_init/amdgpu_nbio_ras_fini function code
authoryipechai <YiPeng.Chai@amd.com>
Tue, 8 Feb 2022 02:48:56 +0000 (10:48 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 14 Feb 2022 20:08:41 +0000 (15:08 -0500)
Optimize amdgpu_nbio_ras_late_init/amdgpu_nbio_ras_fini function code.

Signed-off-by: yipechai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

index 6ace2e3..89e61fd 100644 (file)
 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, void *ras_info)
 {
        int r;
-       struct ras_ih_if ih_info = {
-               .cb = NULL,
-       };
-       struct ras_fs_if fs_info = {
-               .sysfs_name = "pcie_bif_err_count",
-       };
-
-       if (!adev->nbio.ras_if) {
-               adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
-               if (!adev->nbio.ras_if)
-                       return -ENOMEM;
-               adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
-               adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
-               adev->nbio.ras_if->sub_block_index = 0;
-       }
-       ih_info.head = fs_info.head = *adev->nbio.ras_if;
-       r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
-                                &fs_info, &ih_info);
+       r = amdgpu_ras_block_late_init(adev, adev->nbio.ras_if);
        if (r)
-               goto free;
+               return r;
 
        if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
                r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
@@ -53,30 +36,17 @@ int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, void *ras_info)
                r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
                if (r)
                        goto late_fini;
-       } else {
-               r = 0;
-               goto free;
        }
 
        return 0;
 late_fini:
-       amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);
-free:
-       kfree(adev->nbio.ras_if);
-       adev->nbio.ras_if = NULL;
+       amdgpu_ras_block_late_fini(adev, adev->nbio.ras_if);
        return r;
 }
 
 void amdgpu_nbio_ras_fini(struct amdgpu_device *adev)
 {
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF) &&
-                       adev->nbio.ras_if) {
-               struct ras_common_if *ras_if = adev->nbio.ras_if;
-               struct ras_ih_if ih_info = {
-                       .cb = NULL,
-               };
-
-               amdgpu_ras_late_fini(adev, ras_if, &ih_info);
-               kfree(ras_if);
-       }
+                       adev->nbio.ras_if)
+               amdgpu_ras_block_late_fini(adev, adev->nbio.ras_if);
 }
index 877b0e0..75f5fda 100644 (file)
@@ -2301,6 +2301,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev)
                if (!adev->gmc.xgmi.connected_to_cpu) {
                        adev->nbio.ras = &nbio_v7_4_ras;
                        amdgpu_ras_register_ras_block(adev, &adev->nbio.ras->ras_block);
+                       adev->nbio.ras_if = &adev->nbio.ras->ras_block.ras_comm;
                }
                break;
        default:
index c7cca87..1476857 100644 (file)
@@ -667,6 +667,7 @@ struct amdgpu_nbio_ras nbio_v7_4_ras = {
                .ras_comm = {
                        .name = "pcie_bif",
                        .block = AMDGPU_RAS_BLOCK__PCIE_BIF,
+                       .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
                },
                .hw_ops = &nbio_v7_4_ras_hw_ops,
                .ras_late_init = amdgpu_nbio_ras_late_init,