arm64: dts: mediatek: mt6795: Add nodes for I2C controllers
authorAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Mon, 27 Mar 2023 08:36:35 +0000 (10:36 +0200)
committerMatthias Brugger <matthias.bgg@gmail.com>
Sun, 2 Apr 2023 17:24:25 +0000 (19:24 +0200)
Add all four I2C controller nodes but keep them in disabled state as
usage is board-dependant.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230327083647.22017-6-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
arch/arm64/boot/dts/mediatek/mt6795.dtsi

index 26d640e..ceb6fc9 100644 (file)
                        status = "disabled";
                };
 
+               i2c0: i2c@11007000 {
+                       compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
+                       reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>;
+                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+                       clock-div = <16>;
+                       clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
+                       clock-names = "main", "dma";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@11008000 {
+                       compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
+                       reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>;
+                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
+                       clock-div = <16>;
+                       clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
+                       clock-names = "main", "dma";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@11009000 {
+                       compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
+                       reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>;
+                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
+                       clock-div = <16>;
+                       clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
+                       clock-names = "main", "dma";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c3: i2c@11010000 {
+                       compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
+                       reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>;
+                       interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
+                       clock-div = <16>;
+                       clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>;
+                       clock-names = "main", "dma";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c4: i2c@11011000 {
+                       compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c";
+                       reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>;
+                       interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
+                       clock-div = <16>;
+                       clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>;
+                       clock-names = "main", "dma";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                mmc0: mmc@11230000 {
                        compatible = "mediatek,mt6795-mmc";
                        reg = <0 0x11230000 0 0x1000>;