AMDGPU: Fix some incorrect FUNC-LABEL checks

diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
index 3f61aca713e19ca95904ba52a2b64e5c4b774861..f526ad3ca03b87f9acbcde622e6d6a76b8da72ec 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv.f16.ll
@@ -227,7 +227,7 @@ entry:
   ret void
 }
 
-; FUNC-LABEL: {{^}}div_afn_2_x_pat_f16:
+; SI-LABEL: {{^}}div_afn_2_x_pat_f16:
 ; SI: v_mul_f32_e32 v{{[0-9]+}}, 0.5, v{{[0-9]+}}
 
 ; GFX8_9_10: v_mul_f16_e32 [[MUL:v[0-9]+]], 0.5, v{{[0-9]+}}
@@ -239,7 +239,7 @@ define amdgpu_kernel void @div_afn_2_x_pat_f16(half addrspace(1)* %out) #0 {
   ret void
 }
 
-; FUNC-LABEL: {{^}}div_afn_k_x_pat_f16:
+; SI-LABEL: {{^}}div_afn_k_x_pat_f16:
 ; SI: v_mul_f32_e32 v{{[0-9]+}}, 0x3dcccccd, v{{[0-9]+}}
 
 ; GFX8_9_10: v_mul_f16_e32 [[MUL:v[0-9]+]], 0x2e66, v{{[0-9]+}}
@@ -251,7 +251,7 @@ define amdgpu_kernel void @div_afn_k_x_pat_f16(half addrspace(1)* %out) #0 {
   ret void
 }
 
-; FUNC-LABEL: {{^}}div_afn_neg_k_x_pat_f16:
+; SI-LABEL: {{^}}div_afn_neg_k_x_pat_f16:
 ; SI: v_mul_f32_e32 v{{[0-9]+}}, 0xbdcccccd, v{{[0-9]+}}
 
 ; GFX8_9_10: v_mul_f16_e32 [[MUL:v[0-9]+]], 0xae66, v{{[0-9]+}}

diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
index 80f0a373fb4b5fd95997795ebd416c6d4a88c0df..a977c2ebd746b9a951d8ba08b5cb1ec07c9b6b9e 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
@@ -2,7 +2,7 @@
 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN-UNSAFE %s
 
-; FUNC-LABEL: {{^}}fptrunc_f64_to_f32:
+; GCN-LABEL: {{^}}fptrunc_f64_to_f32:
 ; GCN: v_cvt_f32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
 define amdgpu_kernel void @fptrunc_f64_to_f32(float addrspace(1)* %out, double %in) {
   %result = fptrunc double %in to float
@@ -10,7 +10,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f32(float addrspace(1)* %out, double %
   ret void
 }
 
-; FUNC-LABEL: {{^}}fptrunc_f64_to_f16:
+; GCN-LABEL: {{^}}fptrunc_f64_to_f16:
 ; GCN-NOT: v_cvt
 ; GCN-UNSAFE: v_cvt_f32_f64_e32 [[F32:v[0-9]+]]
 ; GCN-UNSAFE: v_cvt_f16_f32_e32 v{{[0-9]+}}, [[F32]]
@@ -21,7 +21,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(i16 addrspace(1)* %out, double %in
   ret void
 }
 
-; FUNC-LABEL: {{^}}fptrunc_v2f64_to_v2f32:
+; GCN-LABEL: {{^}}fptrunc_v2f64_to_v2f32:
 ; GCN: v_cvt_f32_f64_e32
 ; GCN: v_cvt_f32_f64_e32
 define amdgpu_kernel void @fptrunc_v2f64_to_v2f32(<2 x float> addrspace(1)* %out, <2 x double> %in) {
@@ -30,7 +30,7 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f32(<2 x float> addrspace(1)* %out
   ret void
 }
 
-; FUNC-LABEL: {{^}}fptrunc_v3f64_to_v3f32:
+; GCN-LABEL: {{^}}fptrunc_v3f64_to_v3f32:
 ; GCN: v_cvt_f32_f64_e32
 ; GCN: v_cvt_f32_f64_e32
 ; GCN: v_cvt_f32_f64_e32
@@ -40,7 +40,7 @@ define amdgpu_kernel void @fptrunc_v3f64_to_v3f32(<3 x float> addrspace(1)* %out
   ret void
 }
 
-; FUNC-LABEL: {{^}}fptrunc_v4f64_to_v4f32:
+; GCN-LABEL: {{^}}fptrunc_v4f64_to_v4f32:
 ; GCN: v_cvt_f32_f64_e32
 ; GCN: v_cvt_f32_f64_e32
 ; GCN: v_cvt_f32_f64_e32
@@ -51,7 +51,7 @@ define amdgpu_kernel void @fptrunc_v4f64_to_v4f32(<4 x float> addrspace(1)* %out
   ret void
 }
 
-; FUNC-LABEL: {{^}}fptrunc_v8f64_to_v8f32:
+; GCN-LABEL: {{^}}fptrunc_v8f64_to_v8f32:
 ; GCN: v_cvt_f32_f64_e32
 ; GCN: v_cvt_f32_f64_e32
 ; GCN: v_cvt_f32_f64_e32

diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
index 52820237546ea333e31ba69a9361fb96a4b751a0..f6f3a36d13586f5d860dabba305df928fa4ecab3 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
@@ -2,7 +2,7 @@
 
 declare i32 @llvm.amdgcn.ds.bpermute(i32, i32) #0
 
-; FUNC-LABEL: {{^}}ds_bpermute:
+; CHECK-LABEL: {{^}}ds_bpermute:
 ; CHECK: ds_bpermute_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 define amdgpu_kernel void @ds_bpermute(i32 addrspace(1)* %out, i32 %index, i32 %src) nounwind {
   %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 %index, i32 %src) #0

diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
index c74310fb6ea0f316964c042b3868bd8c157bfbef..e95f49a5fa8e338c1a8673474e94bc21c8dab04c 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN %s
 
-; FUNC-LABEL: {{^}}ds_ordered_add:
+; GCN-LABEL: {{^}}ds_ordered_add:
 ; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
 ; GCN-DAG: s_mov_b32 m0,
 ; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:772 gds
@@ -10,7 +10,7 @@ define amdgpu_kernel void @ds_ordered_add(i32 addrspace(2)* inreg %gds, i32 addr
   ret void
 }
 
-; FUNC-LABEL: {{^}}ds_ordered_add_4dw:
+; GCN-LABEL: {{^}}ds_ordered_add_4dw:
 ; GCN-DAG: v_mov_b32_e32 v[[INCR:[0-9]+]], 31
 ; GCN-DAG: s_mov_b32 m0,
 ; GCN: ds_ordered_count v{{[0-9]+}}, v[[INCR]] offset:49924 gds

diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
index d97644262016ea23d424a9cd783d28a7517bcac9..26e82223d7f0ca2dd52fe52877b63dfaab27af34 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll
@@ -3,7 +3,7 @@
 
 declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #0
 
-; FUNC-LABEL: {{^}}ds_swizzle:
+; CHECK-LABEL: {{^}}ds_swizzle:
 ; CHECK: ds_swizzle_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:swizzle(BITMASK_PERM,"00p11")
 define amdgpu_kernel void @ds_swizzle(i32 addrspace(1)* %out, i32 %src) nounwind {
   %swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100) #0

diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
index 39370e41e8aa9953da65d52ee011dc61b79a84f1..d29ae5ba4374c35634d4cbf613f60975cac9ef35 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll
@@ -3,7 +3,7 @@
 
 declare i32 @llvm.amdgcn.sffbh.i32(i32) #1
 
-; FUNC-LABEL: {{^}}s_flbit:
+; GCN-LABEL: {{^}}s_flbit:
 ; GCN: s_load_dword [[VAL:s[0-9]+]],
 ; GCN: s_flbit_i32 [[SRESULT:s[0-9]+]], [[VAL]]
 ; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
@@ -14,7 +14,7 @@ define amdgpu_kernel void @s_flbit(i32 addrspace(1)* noalias %out, i32 %val) #0
   ret void
 }
 
-; FUNC-LABEL: {{^}}v_flbit:
+; GCN-LABEL: {{^}}v_flbit:
 ; GCN: buffer_load_dword [[VAL:v[0-9]+]],
 ; GCN: v_ffbh_i32_e32 [[RESULT:v[0-9]+]], [[VAL]]
 ; GCN: buffer_store_dword [[RESULT]],

diff --git a/llvm/test/CodeGen/AMDGPU/shl_add_constant.ll b/llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
index 9f1303479130f48995017f4f7db7b325ea38c37f..098c69f7e21a9d11e851f731fed01fae141277f6 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/shl_add_constant.ll
@@ -4,7 +4,7 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1
 
 ; Test with inline immediate
 
-; FUNC-LABEL: {{^}}shl_2_add_9_i32:
+; SI-LABEL: {{^}}shl_2_add_9_i32:
 ; SI: v_lshlrev_b32_e32  [[REG:v[0-9]+]], 2, {{v[0-9]+}}
 ; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 36, [[REG]]
 ; SI: buffer_store_dword [[RESULT]]
@@ -19,7 +19,7 @@ define amdgpu_kernel void @shl_2_add_9_i32(i32 addrspace(1)* %out, i32 addrspace
   ret void
 }
 
-; FUNC-LABEL: {{^}}shl_2_add_9_i32_2_add_uses:
+; SI-LABEL: {{^}}shl_2_add_9_i32_2_add_uses:
 ; SI-DAG: v_add_i32_e32 [[ADDREG:v[0-9]+]], vcc, 9, {{v[0-9]+}}
 ; SI-DAG: v_lshlrev_b32_e32 [[SHLREG:v[0-9]+]], 2, {{v[0-9]+}}
 ; SI-DAG: buffer_store_dword [[ADDREG]]
@@ -38,7 +38,7 @@ define amdgpu_kernel void @shl_2_add_9_i32_2_add_uses(i32 addrspace(1)* %out0, i
 
 ; Test with add literal constant
 
-; FUNC-LABEL: {{^}}shl_2_add_999_i32:
+; SI-LABEL: {{^}}shl_2_add_999_i32:
 ; SI: v_lshlrev_b32_e32  [[REG:v[0-9]+]], 2, {{v[0-9]+}}
 ; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, 0xf9c, [[REG]]
 ; SI: buffer_store_dword [[RESULT]]
@@ -53,7 +53,7 @@ define amdgpu_kernel void @shl_2_add_999_i32(i32 addrspace(1)* %out, i32 addrspa
   ret void
 }
 
-; FUNC-LABEL: {{^}}test_add_shl_add_constant:
+; SI-LABEL: {{^}}test_add_shl_add_constant:
 ; SI-DAG: s_load_dwordx2 s{{\[}}[[X:[0-9]+]]:[[Y:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x13
 ; SI-DAG: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 3
 ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[SHL3]], s[[Y]]
@@ -68,7 +68,7 @@ define amdgpu_kernel void @test_add_shl_add_constant(i32 addrspace(1)* %out, [8
   ret void
 }
 
-; FUNC-LABEL: {{^}}test_add_shl_add_constant_inv:
+; SI-LABEL: {{^}}test_add_shl_add_constant_inv:
 ; SI-DAG: s_load_dwordx2 s{{\[}}[[X:[0-9]+]]:[[Y:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x13
 ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], s[[X]], 3
 ; SI: s_add_i32 [[TMP:s[0-9]+]], [[SHL3]], s[[Y]]

diff --git a/llvm/test/CodeGen/AMDGPU/sitofp.f16.ll b/llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
index 3a3e0def36c9e37fccf593221346a07b1a217e7d..144c6933962e9927bac6626ebf9b41f7979ab40b 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
@@ -94,7 +94,7 @@ entry:
   ret void
 }
 
-; FUNC-LABEL: {{^}}s_sint_to_fp_i1_to_f16:
+; GCN-LABEL: {{^}}s_sint_to_fp_i1_to_f16:
 ; GCN-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 1.0, {{v[0-9]+}}
 ; GCN-DAG: v_cmp_le_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, {{v[0-9]+}}
 ; GCN: s_xor_b64 [[R_CMP:s\[[0-9]+:[0-9]+\]]], [[CMP1]], [[CMP0]]

diff --git a/llvm/test/CodeGen/AMDGPU/uitofp.f16.ll b/llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
index 1a42618d5a70f1497c3428d20b74b5f6628cac1c..99a3141ab54867f45c05dfcaf86d2056687caec0 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
@@ -93,7 +93,7 @@ entry:
   ret void
 }
 
-; FUNC-LABEL: {{^}}s_uint_to_fp_i1_to_f16:
+; GCN-LABEL: {{^}}s_uint_to_fp_i1_to_f16:
 ; GCN-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 1.0, {{v[0-9]+}}
 ; GCN-DAG: v_cmp_le_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, {{v[0-9]+}}
 ; GCN: s_xor_b64 [[R_CMP:s\[[0-9]+:[0-9]+\]]], [[CMP1]], [[CMP0]]

diff --git a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
index 020f677ee3cfa92b2e3ce36fee4f9e7fed7f5e9c..ea60d0d00432fb395b30e56923c6b5d60d65f9e3 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
+++ b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
@@ -29,7 +29,7 @@ define amdgpu_kernel void @global_unaligned_load_store_i16(i16 addrspace(1)* %p,
   ret void
 }
 
-; FUNC-LABEL: {{^}}local_unaligned_load_store_i32:
+; SI-LABEL: {{^}}local_unaligned_load_store_i32:
 
 ; SI: ds_read_u8
 ; SI: ds_read_u8
@@ -80,7 +80,7 @@ define amdgpu_kernel void @global_align2_load_store_i32(i32 addrspace(1)* %p, i3
   ret void
 }
 
-; FUNC-LABEL: {{^}}local_align2_load_store_i32:
+; GCN-LABEL: {{^}}local_align2_load_store_i32:
 ; GCN: ds_read_u16
 ; GCN: ds_read_u16
 ; GCN: ds_write_b16
@@ -91,7 +91,7 @@ define amdgpu_kernel void @local_align2_load_store_i32(i32 addrspace(3)* %p, i32
   ret void
 }
 
-; FUNC-LABEL: {{^}}local_unaligned_load_store_i64:
+; SI-LABEL: {{^}}local_unaligned_load_store_i64:
 ; SI: ds_read_u8
 ; SI: ds_read_u8
 ; SI: ds_read_u8
@@ -245,7 +245,7 @@ define amdgpu_kernel void @unaligned_load_store_i64_global(i64 addrspace(1)* %p,
   ret void
 }
 
-; FUNC-LABEL: {{^}}local_unaligned_load_store_v4i32:
+; GCN-LABEL: {{^}}local_unaligned_load_store_v4i32:
 ; GCN: ds_read_u8
 ; GCN: ds_read_u8
 ; GCN: ds_read_u8
@@ -335,7 +335,7 @@ define amdgpu_kernel void @global_unaligned_load_store_v4i32(<4 x i32> addrspace
   ret void
 }
 
-; FUNC-LABEL: {{^}}local_load_i64_align_4:
+; GCN-LABEL: {{^}}local_load_i64_align_4:
 ; GCN: ds_read2_b32
 define amdgpu_kernel void @local_load_i64_align_4(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
   %val = load i64, i64 addrspace(3)* %in, align 4
@@ -343,7 +343,7 @@ define amdgpu_kernel void @local_load_i64_align_4(i64 addrspace(1)* nocapture %o
   ret void
 }
 
-; FUNC-LABEL: {{^}}local_load_i64_align_4_with_offset
+; GCN-LABEL: {{^}}local_load_i64_align_4_with_offset
 ; GCN: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:8 offset1:9
 define amdgpu_kernel void @local_load_i64_align_4_with_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
   %ptr = getelementptr i64, i64 addrspace(3)* %in, i32 4
@@ -352,7 +352,7 @@ define amdgpu_kernel void @local_load_i64_align_4_with_offset(i64 addrspace(1)*
   ret void
 }
 
-; FUNC-LABEL: {{^}}local_load_i64_align_4_with_split_offset:
+; GCN-LABEL: {{^}}local_load_i64_align_4_with_split_offset:
 ; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits
 ; GCN: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset1:1
 ; GCN: s_endpgm
@@ -365,7 +365,7 @@ define amdgpu_kernel void @local_load_i64_align_4_with_split_offset(i64 addrspac
   ret void
 }
 
-; FUNC-LABEL: {{^}}local_load_i64_align_1:
+; GCN-LABEL: {{^}}local_load_i64_align_1:
 ; GCN: ds_read_u8
 ; GCN: ds_read_u8
 ; GCN: ds_read_u8
@@ -381,14 +381,14 @@ define amdgpu_kernel void @local_load_i64_align_1(i64 addrspace(1)* nocapture %o
   ret void
 }
 
-; FUNC-LABEL: {{^}}local_store_i64_align_4:
+; GCN-LABEL: {{^}}local_store_i64_align_4:
 ; GCN: ds_write2_b32
 define amdgpu_kernel void @local_store_i64_align_4(i64 addrspace(3)* %out, i64 %val) #0 {
   store i64 %val, i64 addrspace(3)* %out, align 4
   ret void
 }
 
-; FUNC-LABEL: {{^}}local_store_i64_align_4_with_offset
+; GCN-LABEL: {{^}}local_store_i64_align_4_with_offset
 ; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:8 offset1:9
 ; GCN: s_endpgm
 define amdgpu_kernel void @local_store_i64_align_4_with_offset(i64 addrspace(3)* %out) #0 {
@@ -397,7 +397,7 @@ define amdgpu_kernel void @local_store_i64_align_4_with_offset(i64 addrspace(3)*
   ret void
 }
 
-; FUNC-LABEL: {{^}}local_store_i64_align_4_with_split_offset:
+; GCN-LABEL: {{^}}local_store_i64_align_4_with_split_offset:
 ; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits
 ; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1
 ; GCN: s_endpgm