int data;
unsigned long dev_offset = 0x10;
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
spin_lock_irqsave(®_rw_lock, flags);
data = rd_reg(MAP_ADDR_MODULE_TOP,
addr + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr);
ulong flags;
unsigned int dev_offset = 0x10;
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
spin_lock_irqsave(®_rw_lock, flags);
wr_reg(MAP_ADDR_MODULE_TOP,
addr + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr, data);
unsigned int dev_offset = 0;
unsigned int tempaddr = 0;
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
spin_lock_irqsave(®_rw_lock, flags);
dev_offset = TOP_DWC_BASE_OFFSET +
reg_maps[MAP_ADDR_MODULE_TOP].phy_addr;
unsigned long dev_offset = 0;
unsigned int tempaddr = 0;
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
spin_lock_irqsave(®_rw_lock, flags);
dev_offset = TOP_DWC_BASE_OFFSET +
reg_maps[MAP_ADDR_MODULE_TOP].phy_addr;
uint32_t term_value =
hdmirx_rd_top(TOP_HPD_PWR5V) & 0x7;
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
wr_reg_hhi_bits(HHI_HDMIRX_PHY_MISC_CNTL2, _BIT(1), enable);
/* set rxsense */
if (enable)
ulong flags;
unsigned long dev_offset = 0;
spin_lock_irqsave(®_rw_lock, flags);
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
dev_offset = TOP_DWC_BASE_OFFSET +
reg_maps[MAP_ADDR_MODULE_TOP].phy_addr;
wr_reg(MAP_ADDR_MODULE_TOP,
unsigned int data32 = 0;
if (enable) {
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
data32 |= 1 << 31; /* DRC_CKS_CHG */
data32 |= 1 << 30; /* DRC_RCV */
data32 |= 0 << 29; /* AUD_TYPE_CHG */
{
int clk = false;
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
/* sqofclk */
clk = hdmirx_rd_top(TOP_MISC_STAT0) & 0x1;
} else {
hdmirx_wr_top(TOP_VID_CNTL2, data32);
}
data32 = 0;
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
/* n_cts_auto_mode: */
/* 0-every ACR packet */
/* 1-on N or CTS value change */
}
/* delay cycles before n/cts update pulse */
data32 |= 7 << 0;
- if (rx.chip_id == CHIP_ID_TL1)
+ if (rx.chip_id >= CHIP_ID_TL1)
hdmirx_wr_top(TOP_TL1_ACR_CNTL2, data32);
else
hdmirx_wr_top(TOP_ACR_CNTL2, data32);
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
data32 = hdmirx_rd_dwc(DWC_HDCP_CTRL);
/* 0: Original behaviour */
/* 1: Balance path delay between non-HDCP and HDCP */
#if 0
void rx_set_term_enable(bool enable)
{
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
/* need to do : for tl1 */
} else
hdmirx_wr_bits_phy(PHY_MAIN_FSM_OVERRIDE1,
{
unsigned int data32;
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
/* need to do : for tl1 */
data32 = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
if (port < E_PORT3) {
unsigned int term_ovr_value;
unsigned int data32;
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
/* enable terminal connect */
data32 = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
if (level) {
((0 << 25) |
(1 << 24) | /* [ 24] Enable gated clock */
(0 << 16)));
- if (rx.chip_id == CHIP_ID_TL1)
+ if (rx.chip_id >= CHIP_ID_TL1)
/* TL1:esm related clk bit9-11 */
hdmirx_wr_bits_top(TOP_CLK_CNTL, MSK(3, 9), 0x7);
else
void hdmirx_hdcp22_esm_rst(void)
{
/* For TL1,the sw_reset_hdcp22 bit is top reg 0x0,bit'12 */
- if (rx.chip_id == CHIP_ID_TL1)
+ if (rx.chip_id >= CHIP_ID_TL1)
hdmirx_wr_top(TOP_SW_RESET, 0x1000);
else
/* For txlx and previous chips,the sw_reset_hdcp22 is bit'8 */
#endif
if ((rx.chip_id == CHIP_ID_TXLX) ||
(rx.chip_id == CHIP_ID_TXHD) ||
- (rx.chip_id == CHIP_ID_TL1)) {
+ (rx.chip_id >= CHIP_ID_TL1)) {
/* [15] hdmirx_aud_pll4x_en override enable */
/* [14] hdmirx_aud_pll4x_en override value */
/* [6:5] clk_sel for cts_hdmirx_aud_pll_clk: */
data32 |= 0 << 31; /* [31] disable clkgating */
data32 |= 1 << 17; /* [17] audfifo_rd_en */
data32 |= 1 << 16; /* [16] pktfifo_rd_en */
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
data32 |= 0 << 8; /* [8] tmds_ch2_clk_inv */
data32 |= 0 << 7; /* [7] tmds_ch1_clk_inv */
data32 |= 0 << 6; /* [6] tmds_ch0_clk_inv */
data32 |= acr_mode << 0;
hdmirx_wr_top(TOP_ACR_CNTL_STAT, data32);
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
data32 = 0;
data32 |= 0 << 2;/*meas_mode*/
data32 |= 1 << 1;/*enable*/
{
/* uint32_t data32; */
/* uint32_t cur_cable_clk; */
- if (rx.chip_id == CHIP_ID_TL1)
+ if (rx.chip_id >= CHIP_ID_TL1)
aml_phy_bw_switch();
else
snps_phyg3_init();
if (clk_rate != rx.phy.clk_rate) {
changed = true;
- if (rx.chip_id != CHIP_ID_TL1) {
+ if (rx.chip_id < CHIP_ID_TL1) {
for (i = 0; i < 3; i++) {
error = hdmirx_wr_bits_phy(PHY_CDR_CTRL_CNT,
CLK_RATE_BIT, clk_rate);
hdmirx_20_init();
DWC_init();
hdmirx_irq_hdcp_enable(true);
- if (rx.chip_id == CHIP_ID_TL1)
+ if (rx.chip_id >= CHIP_ID_TL1)
aml_phy_switch_port();
hdmirx_phy_init();
hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value);
packet_init();
if (rx.chip_id != CHIP_ID_TXHD)
hdmirx_20_init();
- if (rx.chip_id == CHIP_ID_TL1)
+ if (rx.chip_id >= CHIP_ID_TL1)
aml_phy_switch_port();
hdmirx_phy_init();
hdmirx_wr_top(TOP_PORT_SEL, 0x10);
int tmp = 0;
/*unsigned int od, od2;*/
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
if (en) {
/* AUD_CLK=N/CTS*TMDS_CLK */
/* bandgap enable */
if (clk_src == TOP_HDMI_TMDSCLK)
tmp_data = hdmirx_rd_top(TOP_METER_HDMI_STAT);
else if (clk_src == TOP_HDMI_CABLECLK) {
- if (rx.chip_id == CHIP_ID_TL1)
+ if (rx.chip_id >= CHIP_ID_TL1)
tmp_data = hdmirx_rd_top(TOP_METER_CABLE_STAT);
} else if (clk_src == TOP_HDMI_AUDIOCLK) {
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
/*get audio clk*/
tmp_data = hdmirx_rd_top(TOP_AUDMEAS_REF_CYCLES_STAT0);
tmp_data2 = hdmirx_rd_top(TOP_AUDMEAS_REF_CYCLES_STAT1);
*/
if (clksrc == MEASURE_CLK_CABLE) {
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
clock = meson_clk_measure(30);
/*clock = rx_get_clock(TOP_HDMI_CABLECLK);*/
}
} else if (clksrc == MEASURE_CLK_TMDS) {
- if (rx.chip_id == CHIP_ID_TL1)
+ if (rx.chip_id >= CHIP_ID_TL1)
clock = meson_clk_measure(63);
else {
clock = meson_clk_measure(25);
} else if (clksrc == MEASURE_CLK_PIXEL) {
clock = meson_clk_measure(29);
} else if (clksrc == MEASURE_CLK_AUD_PLL) {
- if (rx.chip_id == CHIP_ID_TL1)
+ if (rx.chip_id >= CHIP_ID_TL1)
clock = meson_clk_measure(74);/*audio vid out*/
else
clock = meson_clk_measure(24);
} else if (clksrc == MEASURE_CLK_AUD_DIV) {
- if (rx.chip_id == CHIP_ID_TL1)
+ if (rx.chip_id >= CHIP_ID_TL1)
clock = meson_clk_measure(67);/*apll_clk_audio*/
else
clock = meson_clk_measure(98);
} else if (clksrc == MEASURE_CLK_MPLL) {
- if (rx.chip_id == CHIP_ID_TL1)
+ if (rx.chip_id >= CHIP_ID_TL1)
clock = meson_clk_measure(29);/*apll_clk_out_div*/
else
clock = meson_clk_measure(27);
i = i + 4;
}
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
for (i = 0x25; i <= 0x84;) {
rx_pr("[0x%-3x]", i);
rx_pr("0x%-8x", hdmirx_rd_top(i));
i = i + 4;
}
- } else if (rx.chip_id == CHIP_ID_TL1) {
+ } else if (rx.chip_id >= CHIP_ID_TL1) {
/* dump phy register */
rx_pr("\n***AML PHY registers***\n");
for (i = HHI_HDMIRX_APLL_CNTL0;
uint32_t phy_pll_rate = (hdmirx_rd_phy(PHY_MAINFSM_STATUS1)>>9)&0x3;
uint32_t aud_pll_cntl = (rd_reg_hhi(HHI_AUD_PLL_CNTL6)>>28)&0x3;
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
/* need to do something ...*/
} else {
if (req_clk > PHY_REQUEST_CLK_MAX ||
uint32_t bw;
uint32_t cab_clk = cableclk;
- if (rx.chip_id != CHIP_ID_TL1)
+ if (rx.chip_id < CHIP_ID_TL1)
return phy_frq_band_2;
/* rx_pr("cable clk=%d, clkrate=%d\n", cableclk, clkrate); */
static uint32_t time_cnt;
static uint32_t array_cnt;
- if ((rx.chip_id != CHIP_ID_TL1) ||
+ if ((rx.chip_id < CHIP_ID_TL1) ||
(!find_best_eq))
return;
if ((find_best_eq >= 0x7777) ||
if (force_vic)
return true;
- if (rx.chip_id == CHIP_ID_TL1)
+ if (rx.chip_id >= CHIP_ID_TL1)
return (aml_phy_tmds_valid() == 1) ? true : false;
else
return (rx_get_pll_lock_sts() == 1) ? true : false;
hdmirx_phy_pddq(0);
else
hdmirx_phy_pddq(1);
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
/*the enable of these regs are in phy init*/
if (onoff == 0) {
wr_reg_hhi_bits(HHI_HDMIRX_APLL_CNTL0, _BIT(28), onoff);
{
unsigned int data;
- if (rx.chip_id != CHIP_ID_TL1)
+ if (rx.chip_id < CHIP_ID_TL1)
return;
if (rx.empbuff.pg_addr) {
unsigned int data, data2;
unsigned int i = 0;
- if (rx.chip_id != CHIP_ID_TL1)
+ if (rx.chip_id < CHIP_ID_TL1)
return;
if (rx.empbuff.pg_addr) {
void hdmirx_init_params(void)
{
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
clk_unstable_max = 10;
esd_phy_rst_max = 20;
stable_check_lvl = 0x7df;
}
}
- if (rx.chip_id != CHIP_ID_TL1) {
+ if (rx.chip_id < CHIP_ID_TL1) {
rx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT);
if (rx_top_intr_stat & _BIT(31))
irq_need_clr = 1;
rx_pr("[irq] FIFO MIN\n");
}
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
if (rx_get_bits(intr_pedc,
_BIT(9)) != 0) {
if (log_level & 0x400)
hdmirx_wr_top(TOP_INTR_STAT_CLR, hdmirx_top_intr_stat);
/* modify interrupt flow for isr loading */
/* top interrupt handler */
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
if (hdmirx_top_intr_stat & (1 << 29))
if (log_level & 0x100)
rx_pr("[isr] sqofclk_fall\n");
rx_pr("[isr] enc fall\n");
/* must clear ip interrupt quickly */
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
hdmirx_top_intr_stat &= 0x1;
} else {
hdmirx_top_intr_stat &= (~(1 << 30));
}
}
- if (rx.chip_id != CHIP_ID_TL1) {
+ if (rx.chip_id < CHIP_ID_TL1) {
if (error == 1)
goto reisr;
} else {
ulong timestap;
uint32_t ch0, ch1, ch2;
- if (rx.chip_id != CHIP_ID_TL1)
+ if (rx.chip_id < CHIP_ID_TL1)
return;
timestap = get_seconds();
break;
case ERR_PHY_UNLOCK:
if (err_dbg_cnt == 0) {
- if (rx.chip_id != CHIP_ID_TL1)
+ if (rx.chip_id < CHIP_ID_TL1)
rx_pr("EQ = %d-%d-%d\n",
eq_ch0.bestsetting,
eq_ch1.bestsetting,
uint32_t val0, val1, val2;
rx_pr("[PHY info]\n");
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
rx_get_error_cnt(&val0, &val1, &val2);
rx_pr("err cnt- ch0: %d,ch1:%d ch2:%d\n", val0, val1, val2);
rx_pr("PLL_LCK_STS(tmds valid) = 0x%x\n",
rx_pr(" CA=%u\n", a.auds_ch_alloc);
rx_pr("CTS=%d, N=%d,", a.cts, a.n);
rx_pr("acr clk=%d\n", a.arc);
- if (rx.chip_id == CHIP_ID_TL1) {
+ if (rx.chip_id >= CHIP_ID_TL1) {
rx_get_audio_N_CTS(&val0, &val1);
rx_pr("top CTS:%d, N:%d\n", val1, val0);
}