return x;
}
+static inline int ppc_inst_primary_opcode(u32 x)
+{
+ return ppc_inst_val(x) >> 26;
+}
+
#endif /* _ASM_POWERPC_INST_H */
}
#ifdef CONFIG_SPE
- if ((ppc_inst_val(instr) >> 26) == 0x4) {
+ if (ppc_inst_primary_opcode(instr) == 0x4) {
int reg = (ppc_inst_val(instr) >> 21) & 0x1f;
PPC_WARN_ALIGNMENT(spe, regs);
return emulate_spe(regs, reg, instr);
#include <asm/processor.h>
#include <asm/switch_to.h>
#include <linux/uaccess.h>
+#include <asm/inst.h>
/* Functions in vector.S */
extern void vaddfp(vector128 *dst, vector128 *a, vector128 *b);
return -EFAULT;
word = ppc_inst_val(instr);
- if ((word >> 26) != 4)
+ if (ppc_inst_primary_opcode(instr) != 4)
return -EINVAL; /* not an altivec instruction */
vd = (word >> 21) & 0x1f;
va = (word >> 16) & 0x1f;
*/
bool is_conditional_branch(unsigned int instr)
{
- unsigned int opcode = instr >> 26;
+ unsigned int opcode = ppc_inst_primary_opcode(instr);
if (opcode == 16) /* bc, bca, bcl, bcla */
return true;
static unsigned int branch_opcode(unsigned int instr)
{
- return (instr >> 26) & 0x3F;
+ return ppc_inst_primary_opcode(instr) & 0x3F;
}
static int instr_is_branch_iform(unsigned int instr)
word = ppc_inst_val(instr);
op->type = COMPUTE;
- opcode = instr >> 26;
+ opcode = ppc_inst_primary_opcode(instr);
switch (opcode) {
case 16: /* bc */
op->type = BRANCH;
#include <asm/siginfo.h>
#include <asm/debug.h>
#include <asm/kup.h>
+#include <asm/inst.h>
/*
* Check whether the instruction inst is a store using
if (((ppc_inst_val(inst) >> 16) & 0x1f) != 1)
return false;
/* check major opcode */
- switch (inst >> 26) {
+ switch (ppc_inst_primary_opcode(inst)) {
case OP_STWU:
case OP_STBU:
case OP_STHU: