[RISCV][AArch64] Pre-commit tests for D124711. NFC

diff --git a/llvm/test/CodeGen/AArch64/pr55201.ll b/llvm/test/CodeGen/AArch64/pr55201.ll
new file mode 100644 (file)
index 0000000..52f7cc0
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr55201.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s
+
+define i32 @f(i32 %x) {
+; CHECK-LABEL: f:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ror w8, w0, #27
+; CHECK-NEXT:    orr w0, w8, #0x20
+; CHECK-NEXT:    ret
+  %or1 = or i32 %x, 1
+  %sh1 = shl i32 %or1, 5
+  %sh2 = lshr i32 %x, 27
+  %1 = and i32 %sh2, 1
+  %r = or i32 %sh1, %1
+  ret i32 %r
+}

diff --git a/llvm/test/CodeGen/RISCV/pr55201.ll b/llvm/test/CodeGen/RISCV/pr55201.ll
new file mode 100644 (file)
index 0000000..7dc9c37
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr55201.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s
+
+define i32 @f(i32 %x) {
+; CHECK-LABEL: f:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    rori a0, a0, 27
+; CHECK-NEXT:    ori a0, a0, 32
+; CHECK-NEXT:    ret
+  %or1 = or i32 %x, 1
+  %sh1 = shl i32 %or1, 5
+  %sh2 = lshr i32 %x, 27
+  %1 = and i32 %sh2, 1
+  %r = or i32 %sh1, %1
+  ret i32 %r
+}