-# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_anyext(i8* %addr) {
- entry:
- ret void
- }
- define void @test_anyext_with_copy(i8* %addr) {
- entry:
- ret void
- }
- define void @test_signext(i8* %addr) {
- entry:
- ret void
- }
- define void @test_zeroext(i8* %addr) {
- entry:
- ret void
- }
- define void @test_2anyext(i8* %addr) {
- entry:
- ret void
- }
- define void @test_1anyext_1signext(i8* %addr) {
- entry:
- ret void
- }
- define void @test_1xor_1signext(i8* %addr) {
- entry:
- ret void
- }
- define void @test_1anyext_1zeroext(i8* %addr) {
- entry:
- ret void
- }
- define void @test_1signext_1zeroext(i8* %addr) {
- entry:
- ret void
- }
- define void @test_1anyext64_1signext32(i8* %addr) {
- entry:
- ret void
- }
- define void @test_1anyext32_1signext64(i8* %addr) {
- entry:
- ret void
- }
- define void @test_2anyext32_1signext64(i8* %addr) {
- entry:
- ret void
- }
- define void @test_multiblock_anyext(i8* %addr) {
- entry:
- ret void
- }
- define void @test_multiblock_signext(i8* %addr) {
- entry:
- ret void
- }
- define void @test_multiblock_zeroext(i8* %addr) {
- entry:
- ret void
- }
- define void @test_multiblock_2anyext(i8* %addr) {
- entry:
- ret void
- }
- define void @test_multiblock_1anyext64_1signext32(i8* %addr) {
- entry:
- ret void
- }
- define void @test_multiblock_1anyext32_1signext64(i8* %addr) {
- entry:
- ret void
- }
- define void @test_multiblock_2anyext32_1signext64(i8* %addr) {
- entry:
- ret void
- }
-...
-
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
---
name: test_anyext
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
; CHECK-LABEL: name: test_anyext
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: $w0 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1
$w0 = COPY %2
...
---
name: test_anyext_with_copy
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
- ; CHECK-LABEL: name: test_anyext
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
+ ; CHECK-LABEL: name: test_anyext_with_copy
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: $w0 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s8) = COPY %1
%3:_(s32) = G_ANYEXT %1
$w0 = COPY %3
---
name: test_signext
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
; CHECK-LABEL: name: test_signext
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_SEXT %1
$w0 = COPY %2
...
---
name: test_zeroext
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
; CHECK-LABEL: name: test_zeroext
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ZEXT %1
$w0 = COPY %2
...
---
name: test_2anyext
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
; CHECK-LABEL: name: test_2anyext
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
- ; CHECK: $w1 = COPY [[T1]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: $w0 = COPY [[LOAD]](s32)
+ ; CHECK: $w1 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1
%3:_(s32) = G_ANYEXT %1
$w0 = COPY %2
---
name: test_1anyext_1signext
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
; CHECK-LABEL: name: test_1anyext_1signext
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
- ; CHECK: $w1 = COPY [[T1]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
+ ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1
%3:_(s32) = G_SEXT %1
$w0 = COPY %2
---
name: test_1xor_1signext
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
; CHECK-LABEL: name: test_1xor_1signext
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
- ; CHECK: [[T3:%[0-9]+]]:_(s8) = G_XOR [[T2]], {{%[0-9]+}}
- ; CHECK: [[T4:%[0-9]+]]:_(s32) = G_ANYEXT [[T3]]
- ; CHECK: $w0 = COPY [[T4]](s32)
- ; CHECK: $w1 = COPY [[T1]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s32)
+ ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1
+ ; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[TRUNC]], [[C]]
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s8)
+ ; CHECK: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s8) = G_CONSTANT i8 -1
%3:_(s8) = G_XOR %1, %2
%5:_(s32) = G_ANYEXT %3
---
name: test_1anyext_1zeroext
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
; CHECK-LABEL: name: test_1anyext_1zeroext
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
- ; CHECK: $w1 = COPY [[T1]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
+ ; CHECK: $w1 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1
%3:_(s32) = G_ZEXT %1
$w0 = COPY %2
---
name: test_1signext_1zeroext
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
; CHECK-LABEL: name: test_1signext_1zeroext
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
- ; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ZEXT [[T2]]
- ; CHECK: $w0 = COPY [[T3]](s32)
- ; CHECK: $w1 = COPY [[T1]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s32)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s8)
+ ; CHECK: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ZEXT %1
%3:_(s32) = G_SEXT %1
$w0 = COPY %2
---
name: test_1anyext64_1signext32
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
; CHECK-LABEL: name: test_1anyext64_1signext32
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK-NOT: [[T1]]
- ; CHECK: [[T2:%[0-9]+]]:_(s64) = G_ANYEXT [[T1]]
- ; CHECK-NOT: [[T1]]
- ; CHECK: $x0 = COPY [[T2]](s64)
- ; CHECK: $w1 = COPY [[T1]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SEXTLOAD]](s32)
+ ; CHECK: $x0 = COPY [[ANYEXT]](s64)
+ ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s64) = G_ANYEXT %1
%3:_(s32) = G_SEXT %1
$x0 = COPY %2
---
name: test_1anyext32_1signext64
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
; CHECK-LABEL: name: test_1anyext32_1signext64
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
- ; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
- ; CHECK: $w0 = COPY [[T3]](s32)
- ; CHECK: $x1 = COPY [[T1]](s64)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s64)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
+ ; CHECK: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK: $x1 = COPY [[SEXTLOAD]](s64)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1
%3:_(s64) = G_SEXT %1
$w0 = COPY %2
---
name: test_2anyext32_1signext64
body: |
- bb.0.entry:
+ bb.0:
liveins: $x0
; CHECK-LABEL: name: test_2anyext32_1signext64
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
- ; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
- ; CHECK: [[T5:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
- ; CHECK: $w0 = COPY [[T3]](s32)
- ; CHECK: $x1 = COPY [[T1]](s64)
- ; CHECK: $w2 = COPY [[T5]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s64)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
+ ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
+ ; CHECK: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK: $x1 = COPY [[SEXTLOAD]](s64)
+ ; CHECK: $w2 = COPY [[ANYEXT1]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1
%3:_(s64) = G_SEXT %1
%4:_(s32) = G_ANYEXT %1
---
name: test_multiblock_anyext
body: |
- bb.0.entry:
+ ; CHECK-LABEL: name: test_multiblock_anyext
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: G_BR %bb.1
+ ; CHECK: bb.1:
+ ; CHECK: $w0 = COPY [[LOAD]](s32)
+ bb.0:
liveins: $x0
- ; CHECK-LABEL: name: test_multiblock_anyext
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: G_BR %bb.1
- ; CHECK: $w0 = COPY [[T1]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
G_BR %bb.1
bb.1:
%2:_(s32) = G_ANYEXT %1
---
name: test_multiblock_signext
body: |
- bb.0.entry:
+ ; CHECK-LABEL: name: test_multiblock_signext
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: G_BR %bb.1
+ ; CHECK: bb.1:
+ ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
+ bb.0:
liveins: $x0
- ; CHECK-LABEL: name: test_multiblock_signext
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
G_BR %bb.1
bb.1:
%2:_(s32) = G_SEXT %1
---
name: test_multiblock_zeroext
body: |
- bb.0.entry:
+ ; CHECK-LABEL: name: test_multiblock_zeroext
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: G_BR %bb.1
+ ; CHECK: bb.1:
+ ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
+ bb.0:
liveins: $x0
- ; CHECK-LABEL: name: test_multiblock_zeroext
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
G_BR %bb.1
bb.1:
%2:_(s32) = G_ZEXT %1
---
name: test_multiblock_2anyext
body: |
- bb.0.entry:
+ ; CHECK-LABEL: name: test_multiblock_2anyext
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: G_BR %bb.1
+ ; CHECK: bb.1:
+ ; CHECK: $w0 = COPY [[LOAD]](s32)
+ ; CHECK: $w1 = COPY [[LOAD]](s32)
+ bb.0:
liveins: $x0
- ; CHECK-LABEL: name: test_multiblock
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
- ; CHECK: $w1 = COPY [[T1]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%2:_(s32) = G_ANYEXT %1
G_BR %bb.1
bb.1:
---
name: test_multiblock_1anyext64_1signext32
body: |
- bb.0.entry:
+ ; CHECK-LABEL: name: test_multiblock_1anyext64_1signext32
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: G_BR %bb.1
+ ; CHECK: bb.1:
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SEXTLOAD]](s32)
+ ; CHECK: $x0 = COPY [[ANYEXT]](s64)
+ ; CHECK: $w1 = COPY [[SEXTLOAD]](s32)
+ bb.0:
liveins: $x0
- ; CHECK-LABEL: name: test_multiblock_1anyext64_1signext32
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: G_BR %bb.1
- ; CHECK: [[T2:%[0-9]+]]:_(s64) = G_ANYEXT [[T1]]
- ; CHECK: $x0 = COPY [[T2]](s64)
- ; CHECK: $w1 = COPY [[T1]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
G_BR %bb.1
bb.1:
%2:_(s64) = G_ANYEXT %1
---
name: test_multiblock_1anyext32_1signext64
body: |
- bb.0.entry:
+ ; CHECK-LABEL: name: test_multiblock_1anyext32_1signext64
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: G_BR %bb.1
+ ; CHECK: bb.1:
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s64)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
+ ; CHECK: $w0 = COPY [[ANYEXT]](s32)
+ ; CHECK: $x1 = COPY [[SEXTLOAD]](s64)
+ bb.0:
liveins: $x0
- ; CHECK-LABEL: name: test_multiblock_1anyext32_1signext64
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: G_BR %bb.1
- ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
- ; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
- ; CHECK: $w0 = COPY [[T3]](s32)
- ; CHECK: $x1 = COPY [[T1]](s64)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
G_BR %bb.1
bb.1:
%2:_(s32) = G_ANYEXT %1
---
name: test_multiblock_2anyext32_1signext64
body: |
- bb.0.entry:
+ ; CHECK-LABEL: name: test_multiblock_2anyext32_1signext64
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s64)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
+ ; CHECK: G_BR %bb.1
+ ; CHECK: bb.1:
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[SEXTLOAD]](s64)
+ ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s8)
+ ; CHECK: $w0 = COPY [[ANYEXT1]](s32)
+ ; CHECK: $x1 = COPY [[SEXTLOAD]](s64)
+ ; CHECK: $w2 = COPY [[ANYEXT]](s32)
+ bb.0:
liveins: $x0
- ; CHECK-LABEL: name: test_multiblock_2anyext32_1signext64
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
- ; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
- ; CHECK: G_BR %bb.1
- ; CHECK: [[T4:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
- ; CHECK: [[T5:%[0-9]+]]:_(s32) = G_ANYEXT [[T4]]
- ; CHECK: $w0 = COPY [[T5]](s32)
- ; CHECK: $x1 = COPY [[T1]](s64)
- ; CHECK: $w2 = COPY [[T3]](s32)
%0:_(p0) = COPY $x0
- %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s8) = G_LOAD %0 :: (load 1)
%4:_(s32) = G_ANYEXT %1
G_BR %bb.1
bb.1:
$x1 = COPY %3
$w2 = COPY %4
...
+---
+name: test_atomic
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$x0' }
+body: |
+ bb.1:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_atomic
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load unordered 2)
+ ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s16)
+ ; CHECK: $w0 = COPY [[ZEXT]](s32)
+ ; CHECK: RET_ReallyLR implicit $w0
+ %0:_(p0) = COPY $x0
+ %1:_(s16) = G_LOAD %0(p0) :: (load unordered 2)
+ %2:_(s32) = G_ZEXT %1(s16)
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+...