surf->htile_size = AddrHtileOut->htileBytes;
surf->htile_slice_size = AddrHtileOut->sliceSize;
surf->htile_alignment = AddrHtileOut->baseAlign;
+ surf->num_htile_levels = level + 1;
}
}
/* HTILE */
ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
+ ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {0};
hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
+ hout.pMipInfo = meta_mip_info;
assert(in->flags.metaPipeUnaligned == 0);
assert(in->flags.metaRbUnaligned == 0);
surf->htile_size = hout.htileBytes;
surf->htile_slice_size = hout.sliceSize;
surf->htile_alignment = hout.baseAlign;
+ surf->num_htile_levels = in->numMipLevels;
+
+ for (unsigned i = 0; i < in->numMipLevels; i++) {
+ surf->u.gfx9.htile_levels[i].offset = meta_mip_info[i].offset;
+ surf->u.gfx9.htile_levels[i].size = meta_mip_info[i].sliceSize;
+
+ if (meta_mip_info[i].inMiptail) {
+ /* GFX10 can only compress the first level
+ * in the mip tail.
+ */
+ surf->num_htile_levels = i + 1;
+ break;
+ }
+ }
+
+ if (!surf->num_htile_levels)
+ surf->htile_size = 0;
+
return 0;
}
/* DCC level info */
struct gfx9_surf_level dcc_levels[RADEON_SURF_MAX_LEVELS];
+
+ /* HTILE level info */
+ struct gfx9_surf_level htile_levels[RADEON_SURF_MAX_LEVELS];
};
struct radeon_surf {
uint32_t htile_size;
uint32_t htile_slice_size;
uint32_t htile_alignment;
+ uint32_t num_htile_levels : 4;
uint32_t cmask_size;
uint32_t cmask_slice_size;