arm64: dts: imx8dxl: add usb1 and usb2 support

There are two chipidea usb controller in 8dxl.
Add usb node at common connect subsystem.
Enable two usb at imx8dxl_evk boards dts.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 82a1c44..bf72732 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -34,6 +34,35 @@ conn_subsys: bus@5b000000 {
                clock-output-names = "conn_ipg_clk";
        };
 
+       usbotg1: usb@5b0d0000 {
+               compatible = "fsl,imx7ulp-usb";
+               reg = <0x5b0d0000 0x200>;
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+               fsl,usbphy = <&usbphy1>;
+               fsl,usbmisc = <&usbmisc1 0>;
+               clocks = <&usb2_lpcg 0>;
+               ahb-burst-config = <0x0>;
+               tx-burst-size-dword = <0x10>;
+               rx-burst-size-dword = <0x10>;
+               power-domains = <&pd IMX_SC_R_USB_0>;
+               status = "disabled";
+       };
+
+       usbmisc1: usbmisc@5b0d0200 {
+               #index-cells = <1>;
+               compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
+               reg = <0x5b0d0200 0x200>;
+       };
+
+       usbphy1: usbphy@5b100000 {
+               compatible = "fsl,imx7ulp-usbphy";
+               reg = <0x5b100000 0x1000>;
+               clocks = <&usb2_lpcg 1>;
+               power-domains = <&pd IMX_SC_R_USB_0_PHY>;
+               status = "disabled";
+       };
+
        usdhc1: mmc@5b010000 {
                interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
                reg = <0x5b010000 0x10000>;
@@ -195,4 +224,14 @@ conn_subsys: bus@5b000000 {
                                     "enet1_lpcg_ipg_s_clk";
                power-domains = <&pd IMX_SC_R_ENET_1>;
        };
+
+       usb2_lpcg: clock-controller@5b270000 {
+               compatible = "fsl,imx8qxp-lpcg";
+               reg = <0x5b270000 0x10000>;
+               #clock-cells = <1>;
+               clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
+               clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
+               clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
+               power-domains = <&pd IMX_SC_R_USB_0_PHY>;
+       };
 };

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index ca2a43e..a91a706 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -266,6 +266,40 @@
        };
 };
 
+&usbphy1 {
+       /* USB eye diagram tests result */
+       fsl,tx-d-cal = <114>;
+       status = "okay";
+};
+
+&usbotg1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usbotg1>;
+       srp-disable;
+       hnp-disable;
+       adp-disable;
+       power-active-high;
+       disable-over-current;
+       status = "okay";
+};
+
+&usbphy2 {
+       /* USB eye diagram tests result */
+       fsl,tx-d-cal = <111>;
+       status = "okay";
+};
+
+&usbotg2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usbotg2>;
+       srp-disable;
+       hnp-disable;
+       adp-disable;
+       power-active-high;
+       disable-over-current;
+       status = "okay";
+};
+
 &usdhc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc1>;

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
index 69c4849..6b416fb 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
@@ -140,3 +140,13 @@
        compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
        interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 };
+
+&usbotg1 {
+       interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+       /*
+        * usbotg1 and usbotg2 share one clock
+        * scfw disable clock access and keep it always on
+        * in case other core (M4) use one of these.
+        */
+       clocks = <&clk_dummy>;
+};