arm64: dts: ti: k3-j721e-main: Add C71x DSP node

The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.

The following firmware name is used by default for the C71x core,
and can be overridden in a board dts file if desired:
    C71x_0 DSP: j7-c71_0-fw

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20200825172145.13186-6-s-anna@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 52f3373..00a36a1 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1375,4 +1375,16 @@
                resets = <&k3_reset 143 1>;
                firmware-name = "j7-c66_1-fw";
        };
+
+       c71_0: dsp@64800000 {
+               compatible = "ti,j721e-c71-dsp";
+               reg = <0x00 0x64800000 0x00 0x00080000>,
+                     <0x00 0x64e00000 0x00 0x0000c000>;
+               reg-names = "l2sram", "l1dram";
+               ti,sci = <&dmsc>;
+               ti,sci-dev-id = <15>;
+               ti,sci-proc-ids = <0x30 0xff>;
+               resets = <&k3_reset 15 1>;
+               firmware-name = "j7-c71_0-fw";
+       };
 };