``experimental-zvfh``
LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`_.
-``experimental-zfa``
- LLVM implements a subset of `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf>`_ (see Chapter 25). Load-immediate instructions (fli.s/fli.d/fli.h) haven't been implemented yet.
-
To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
Vendor Extensions
/// Return true if the operand is a valid floating point rounding mode.
bool isFRMArg() const { return Kind == KindTy::FRM; }
- bool isRTZArg() const { return isFRMArg() && FRM.FRM == RISCVFPRndMode::RTZ; }
bool isImmXLenLI() const {
int64_t Imm;
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
return Error(ErrorLoc, "operand must be a symbol with %tprel_add modifier");
}
- case Match_InvalidRTZArg: {
- SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
- return Error(ErrorLoc, "operand must be 'rtz' floating-point rounding mode");
- }
case Match_InvalidVTypeI: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
return Error(
"'Zhinx' (Half Float in Integer) or "
"'Zhinxmin' (Half Float in Integer Minimal)">;
-def FeatureStdExtZfa
- : SubtargetFeature<"experimental-zfa", "HasStdExtZfa", "true",
- "'Zfa' (Additional Floating-Point)",
- [FeatureStdExtF]>;
-def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
- AssemblerPredicate<(all_of FeatureStdExtZfa),
- "'Zfa' (Additional Floating-Point)">;
-
def FeatureStdExtC
: SubtargetFeature<"c", "HasStdExtC", "true",
"'C' (Compressed Instructions)">;
include "RISCVInstrInfoZc.td"
include "RISCVInstrInfoZk.td"
include "RISCVInstrInfoV.td"
-include "RISCVInstrInfoZfa.td"
include "RISCVInstrInfoZfh.td"
include "RISCVInstrInfoZicbo.td"