Merge tag 'pci-v3.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...

Pull PCI updates from Bjorn Helgaas:
 "The interesting things here are:

   - Turn on Config Request Retry Status Software Visibility.  This
     caused hangs last time, but we included a fix this time.
   - Rework PCI device configuration to use _HPP/_HPX more aggressively
   - Allow PCI devices to be put into D3cold during system suspend
   - Add arm64 PCI support
   - Add APM X-Gene host bridge driver
   - Add TI Keystone host bridge driver
   - Add Xilinx AXI host bridge driver

  More detailed summary:

  Enumeration
    - Check Vendor ID only for Config Request Retry Status (Rajat Jain)
    - Enable Config Request Retry Status when supported (Rajat Jain)
    - Add generic domain handling (Catalin Marinas)
    - Generate uppercase hex for modalias interface class (Ricardo Ribalda Delgado)

  Resource management
    - Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources() (Yinghai Lu)
    - Increase IBM ipr SAS Crocodile BARs to at least system page size (Douglas Lehr)

  PCI device hotplug
    - Prevent NULL dereference during pciehp probe (Andreas Noever)
    - Move _HPP & _HPX handling into core (Bjorn Helgaas)
    - Apply _HPP to PCIe devices as well as PCI (Bjorn Helgaas)
    - Apply _HPP/_HPX to display devices (Bjorn Helgaas)
    - Preserve SERR & PARITY settings when applying _HPP/_HPX (Bjorn Helgaas)
    - Preserve MPS and MRRS settings when applying _HPP/_HPX (Bjorn Helgaas)
    - Apply _HPP/_HPX to all devices, not just hot-added ones (Bjorn Helgaas)
    - Fix wait time in pciehp timeout message (Yinghai Lu)
    - Add more pciehp Slot Control debug output (Yinghai Lu)
    - Stop disabling pciehp notifications during init (Yinghai Lu)

  MSI
    - Remove arch_msi_check_device() (Alexander Gordeev)
    - Rename pci_msi_check_device() to pci_msi_supported() (Alexander Gordeev)
    - Move D0 check into pci_msi_check_device() (Alexander Gordeev)
    - Remove unused kobject from struct msi_desc (Yijing Wang)
    - Remove "pos" from the struct msi_desc msi_attrib (Yijing Wang)
    - Add "msi_bus" sysfs MSI/MSI-X control for endpoints (Yijing Wang)
    - Use __get_cached_msi_msg() instead of get_cached_msi_msg() (Yijing Wang)
    - Use __read_msi_msg() instead of read_msi_msg() (Yijing Wang)
    - Use __write_msi_msg() instead of write_msi_msg() (Yijing Wang)

  Power management
    - Drop unused runtime PM support code for PCIe ports (Rafael J.  Wysocki)
    - Allow PCI devices to be put into D3cold during system suspend (Rafael J. Wysocki)

  AER
    - Add additional AER error strings (Gong Chen)
    - Make <linux/aer.h> standalone includable (Thierry Reding)

  Virtualization
    - Add ACS quirk for Solarflare SFC9120 & SFC9140 (Alex Williamson)
    - Add ACS quirk for Intel 10G NICs (Alex Williamson)
    - Add ACS quirk for AMD A88X southbridge (Marti Raudsepp)
    - Remove unused pci_find_upstream_pcie_bridge(), pci_get_dma_source() (Alex Williamson)
    - Add device flag helpers (Ethan Zhao)
    - Assume all Mellanox devices have broken INTx masking (Gavin Shan)

  Generic host bridge driver
    - Fix ioport_map() for !CONFIG_GENERIC_IOMAP (Liviu Dudau)
    - Add pci_register_io_range() and pci_pio_to_address() (Liviu Dudau)
    - Define PCI_IOBASE as the base of virtual PCI IO space (Liviu Dudau)
    - Fix the conversion of IO ranges into IO resources (Liviu Dudau)
    - Add pci_get_new_domain_nr() and of_get_pci_domain_nr() (Liviu Dudau)
    - Add support for parsing PCI host bridge resources from DT (Liviu Dudau)
    - Add pci_remap_iospace() to map bus I/O resources (Liviu Dudau)
    - Add arm64 architectural support for PCI (Liviu Dudau)

  APM X-Gene
    - Add APM X-Gene PCIe driver (Tanmay Inamdar)
    - Add arm64 DT APM X-Gene PCIe device tree nodes (Tanmay Inamdar)

  Freescale i.MX6
    - Probe in module_init(), not fs_initcall() (Lucas Stach)
    - Delay enabling reference clock for SS until it stabilizes (Tim Harvey)

  Marvell MVEBU
    - Fix uninitialized variable in mvebu_get_tgt_attr() (Thomas Petazzoni)

  NVIDIA Tegra
    - Make sure the PCIe PLL is really reset (Eric Yuen)
    - Add error path tegra_msi_teardown_irq() cleanup (Jisheng Zhang)
    - Fix extended configuration space mapping (Peter Daifuku)
    - Implement resource hierarchy (Thierry Reding)
    - Clear CLKREQ# enable on port disable (Thierry Reding)
    - Add Tegra124 support (Thierry Reding)

  ST Microelectronics SPEAr13xx
    - Pass config resource through reg property (Pratyush Anand)

  Synopsys DesignWare
    - Use NULL instead of false (Fabio Estevam)
    - Parse bus-range property from devicetree (Lucas Stach)
    - Use pci_create_root_bus() instead of pci_scan_root_bus() (Lucas Stach)
    - Remove pci_assign_unassigned_resources() (Lucas Stach)
    - Check private_data validity in single place (Lucas Stach)
    - Setup and clear exactly one MSI at a time (Lucas Stach)
    - Remove open-coded bitmap operations (Lucas Stach)
    - Fix configuration base address when using 'reg' (Minghuan Lian)
    - Fix IO resource end address calculation (Minghuan Lian)
    - Rename get_msi_data() to get_msi_addr() (Minghuan Lian)
    - Add get_msi_data() to pcie_host_ops (Minghuan Lian)
    - Add support for v3.65 hardware (Murali Karicheri)
    - Fold struct pcie_port_info into struct pcie_port (Pratyush Anand)

  TI Keystone
    - Add TI Keystone PCIe driver (Murali Karicheri)
    - Limit MRSS for all downstream devices (Murali Karicheri)
    - Assume controller is already in RC mode (Murali Karicheri)
    - Set device ID based on SoC to support multiple ports (Murali Karicheri)

  Xilinx AXI
    - Add Xilinx AXI PCIe driver (Srikanth Thokala)
    - Fix xilinx_pcie_assign_msi() return value test (Dan Carpenter)

  Miscellaneous
    - Clean up whitespace (Quentin Lambert)
    - Remove assignments from "if" conditions (Quentin Lambert)
    - Move PCI_VENDOR_ID_VMWARE to pci_ids.h (Francesco Ruggeri)
    - x86: Mark DMI tables as initialization data (Mathias Krause)
    - x86: Move __init annotation to the correct place (Mathias Krause)
    - x86: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst (Mathias Krause)
    - x86: Constify pci_mmcfg_probes[] array (Mathias Krause)
    - x86: Mark PCI BIOS initialization code as such (Mathias Krause)
    - Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters (Megan Kamiya)
    - Remove unnecessary variable in pci_add_dynid() (Tobias Klauser)"

* tag 'pci-v3.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (109 commits)
  arm64: dts: Add APM X-Gene PCIe device tree nodes
  PCI: Add ACS quirk for AMD A88X southbridge devices
  PCI: xgene: Add APM X-Gene PCIe driver
  PCI: designware: Remove open-coded bitmap operations
  PCI/MSI: Remove unnecessary temporary variable
  PCI/MSI: Use __write_msi_msg() instead of write_msi_msg()
  MSI/powerpc: Use __read_msi_msg() instead of read_msi_msg()
  PCI/MSI: Use __get_cached_msi_msg() instead of get_cached_msi_msg()
  PCI/MSI: Add "msi_bus" sysfs MSI/MSI-X control for endpoints
  PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib
  PCI/MSI: Remove unused kobject from struct msi_desc
  PCI/MSI: Rename pci_msi_check_device() to pci_msi_supported()
  PCI/MSI: Move D0 check into pci_msi_check_device()
  PCI/MSI: Remove arch_msi_check_device()
  irqchip: armada-370-xp: Remove arch_msi_check_device()
  PCI/MSI/PPC: Remove arch_msi_check_device()
  arm64: Add architectural support for PCI
  PCI: Add pci_remap_iospace() to map bus I/O resources
  of/pci: Add support for parsing PCI host bridge resources from DT
  of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()
  ...

Conflicts:
	arch/arm64/boot/dts/apm-storm.dtsi

diff --cc Documentation/driver-model/devres.txt
Simple merge

diff --cc MAINTAINERS
Simple merge

diff --cc arch/arm64/Kconfig
Simple merge

diff --cc arch/arm64/boot/dts/apm-storm.dtsi
index f391972,403197a..4f6d04d
--- 1/arch/arm64/boot/dts/apm-storm.dtsi
--- 2/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@@ -270,18 -270,170 +270,183 @@@
                                clock-output-names = "rtcclk";
                        };
  
 +                      rngpkaclk: rngpkaclk@17000000 {
 +                              compatible = "apm,xgene-device-clock";
 +                              #clock-cells = <1>;
 +                              clocks = <&socplldiv2 0>;
 +                              reg = <0x0 0x17000000 0x0 0x2000>;
 +                              reg-names = "csr-reg";
 +                              csr-offset = <0xc>;
 +                              csr-mask = <0x10>;
 +                              enable-offset = <0x10>;
 +                              enable-mask = <0x10>;
 +                              clock-output-names = "rngpkaclk";
 +                      };
++
+                       pcie0clk: pcie0clk@1f2bc000 {
+                               status = "disabled";
+                               compatible = "apm,xgene-device-clock";
+                               #clock-cells = <1>;
+                               clocks = <&socplldiv2 0>;
+                               reg = <0x0 0x1f2bc000 0x0 0x1000>;
+                               reg-names = "csr-reg";
+                               clock-output-names = "pcie0clk";
+                       };
+ 
+                       pcie1clk: pcie1clk@1f2cc000 {
+                               status = "disabled";
+                               compatible = "apm,xgene-device-clock";
+                               #clock-cells = <1>;
+                               clocks = <&socplldiv2 0>;
+                               reg = <0x0 0x1f2cc000 0x0 0x1000>;
+                               reg-names = "csr-reg";
+                               clock-output-names = "pcie1clk";
+                       };
+ 
+                       pcie2clk: pcie2clk@1f2dc000 {
+                               status = "disabled";
+                               compatible = "apm,xgene-device-clock";
+                               #clock-cells = <1>;
+                               clocks = <&socplldiv2 0>;
+                               reg = <0x0 0x1f2dc000 0x0 0x1000>;
+                               reg-names = "csr-reg";
+                               clock-output-names = "pcie2clk";
+                       };
+ 
+                       pcie3clk: pcie3clk@1f50c000 {
+                               status = "disabled";
+                               compatible = "apm,xgene-device-clock";
+                               #clock-cells = <1>;
+                               clocks = <&socplldiv2 0>;
+                               reg = <0x0 0x1f50c000 0x0 0x1000>;
+                               reg-names = "csr-reg";
+                               clock-output-names = "pcie3clk";
+                       };
+ 
+                       pcie4clk: pcie4clk@1f51c000 {
+                               status = "disabled";
+                               compatible = "apm,xgene-device-clock";
+                               #clock-cells = <1>;
+                               clocks = <&socplldiv2 0>;
+                               reg = <0x0 0x1f51c000 0x0 0x1000>;
+                               reg-names = "csr-reg";
+                               clock-output-names = "pcie4clk";
+                       };
+               };
+ 
+               pcie0: pcie@1f2b0000 {
+                       status = "disabled";
+                       device_type = "pci";
+                       compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                       #interrupt-cells = <1>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
+                               0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                       reg-names = "csr", "cfg";
+                       ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
+                                 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
+                       dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                     0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
+                                        0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
+                                        0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
+                                        0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
+                       dma-coherent;
+                       clocks = <&pcie0clk 0>;
+               };
+ 
+               pcie1: pcie@1f2c0000 {
+                       status = "disabled";
+                       device_type = "pci";
+                       compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                       #interrupt-cells = <1>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
+                               0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                       reg-names = "csr", "cfg";
+                       ranges = <0x01000000 0x0 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
+                                 0x02000000 0x0 0x80000000 0xd1 0x80000000 0x00 0x80000000>; /* mem */
+                       dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                     0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
+                                        0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
+                                        0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
+                                        0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
+                       dma-coherent;
+                       clocks = <&pcie1clk 0>;
+               };
+ 
+               pcie2: pcie@1f2d0000 {
+                       status = "disabled";
+                       device_type = "pci";
+                       compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                       #interrupt-cells = <1>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
+                                0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                       reg-names = "csr", "cfg";
+                       ranges = <0x01000000 0x0 0x00000000 0x90 0x10000000 0x0 0x00010000   /* io  */
+                                 0x02000000 0x0 0x80000000 0x91 0x80000000 0x0 0x80000000>; /* mem */
+                       dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                     0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
+                                        0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
+                                        0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
+                                        0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
+                       dma-coherent;
+                       clocks = <&pcie2clk 0>;
+               };
+ 
+               pcie3: pcie@1f500000 {
+                       status = "disabled";
+                       device_type = "pci";
+                       compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                       #interrupt-cells = <1>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
+                               0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                       reg-names = "csr", "cfg";
+                       ranges = <0x01000000 0x0 0x00000000 0xa0 0x10000000 0x0 0x00010000   /* io   */
+                                 0x02000000 0x0 0x80000000 0xa1 0x80000000 0x0 0x80000000>; /* mem  */
+                       dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                     0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
+                                        0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
+                                        0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
+                                        0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
+                       dma-coherent;
+                       clocks = <&pcie3clk 0>;
+               };
+ 
+               pcie4: pcie@1f510000 {
+                       status = "disabled";
+                       device_type = "pci";
+                       compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                       #interrupt-cells = <1>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
+                               0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
+                       reg-names = "csr", "cfg";
+                       ranges = <0x01000000 0x0 0x00000000 0xc0 0x10000000 0x0 0x00010000   /* io  */
+                                 0x02000000 0x0 0x80000000 0xc1 0x80000000 0x0 0x80000000>; /* mem */
+                       dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                                     0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
+                                        0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
+                                        0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
+                                        0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
+                       dma-coherent;
+                       clocks = <&pcie4clk 0>;
                };
  
                serial0: serial@1c020000 {

diff --cc arch/arm64/include/asm/Kbuild
Simple merge

diff --cc arch/arm64/include/asm/io.h
Simple merge

diff --cc arch/arm64/include/asm/pgtable.h
Simple merge

diff --cc arch/arm64/kernel/Makefile
Simple merge

diff --cc drivers/irqchip/irq-armada-370-xp.c
Simple merge

diff --cc drivers/net/vmxnet3/vmxnet3_int.h
Simple merge

diff --cc drivers/pci/host/Kconfig
Simple merge

diff --cc drivers/pci/hotplug/acpiphp_glue.c
Simple merge

diff --cc drivers/pci/hotplug/pciehp_hpc.c
Simple merge

diff --cc drivers/pci/probe.c
Simple merge

diff --cc include/linux/pci.h
Simple merge

diff --cc kernel/resource.c
Simple merge