re PR c/6497 (unrecognizable insn:l inux-2.4.19 pre7 kernel comling with gcc-3...

	2002-04-28  Franz Sirl  <Franz.Sirl-kernel@lauterbach.com>

	PR c/6497
	* config/rs6000/rs6000.md (sCC patterns): Remove clobber and use
	result as temporary value.

From-SVN: r52860

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2b13482..55c29e8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2002-04-28  Franz Sirl  <Franz.Sirl-kernel@lauterbach.com>
+
+       PR c/6497
+       * config/rs6000/rs6000.md (sCC patterns): Remove clobber and use
+       result as temporary value.
+
 2002-04-28  Jakub Jelinek  <jakub@redhat.com>
 
        PR c++/6396

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index cb5d164..9763c2f 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11394,13 +11394,12 @@
    (set_attr "length" "12,16")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
        (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                         (match_operand:SI 2 "reg_or_short_operand" "rI"))
-                (match_operand:SI 3 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 4 "=&r"))]
+                (match_operand:SI 3 "gpc_reg_operand" "r")))]
   "! TARGET_POWERPC64"
-  "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
+  "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
   [(set_attr "length" "8")])
 
 (define_insn ""
@@ -11732,15 +11731,14 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
        (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
                         (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
-                (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+                (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
   "! TARGET_POWERPC64"
   "@
-  {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
-  {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
+  {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
+  {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
  [(set_attr "length" "12")])
 
 (define_insn ""
@@ -12041,15 +12039,14 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
        (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
                         (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
-                (match_operand:SI 3 "gpc_reg_operand" "r,r")))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+                (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
   "! TARGET_POWERPC64"
   "@
-   {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
-   {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
+   {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
+   {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
   [(set_attr "length" "8")])
 
 (define_insn ""
@@ -12342,13 +12339,12 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
        (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                        (const_int 0))
-                (match_operand:SI 2 "gpc_reg_operand" "r")))
-   (clobber (match_scratch:SI 3 "=&r"))]
+                (match_operand:SI 2 "gpc_reg_operand" "r")))]
   "! TARGET_POWERPC64"
-  "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
+  "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
   [(set_attr "length" "12")])
 
 (define_insn ""
@@ -12678,15 +12674,14 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
        (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
                         (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
-                (match_operand:SI 3 "reg_or_short_operand" "r,rI")))
-   (clobber (match_scratch:SI 4 "=&r,&r"))]
+                (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
   "! TARGET_POWERPC64"
   "@
-   {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
-   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
+   {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
+   {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
   [(set_attr "length" "8,12")])
 
 (define_insn ""