arm64: dts: renesas: r8a774a1: Add operating points

The RZ/G2M (a.k.a. r8a774a1) comes with two clusters of
processors, similarly to the r8a7796.
The first cluster is made of A57s, the second cluster is
made of A53s.

The operating points for the cluster with the A57s are:

 Frequency | Voltage
-----------|---------
 500 MHz   | 0.82V
 1.0 GHz   | 0.82V
 1.5 GHz   | 0.82V

The operating points for the cluster with the A53s are:

 Frequency | Voltage
-----------|---------
 800 MHz   | 0.82V
 1.0 GHz   | 0.82V
 1.2 GHz   | 0.82V

This patch adds the definitions for the operating points
to the SoC specific DT.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index c2d99f5..4b1332f 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -56,6 +56,48 @@
                clock-frequency = <0>;
        };
 
+       cluster0_opp: opp_table0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1500000000 {
+                       opp-hz = /bits/ 64 <1500000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+       };
+
+       cluster1_opp: opp_table1 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1000000000 {
+                       opp-hz = /bits/ 64 <1000000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+               opp-1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <820000>;
+                       clock-latency-ns = <300000>;
+               };
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -68,6 +110,7 @@
                        next-level-cache = <&L2_CA57>;
                        enable-method = "psci";
                        clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                a57_1: cpu@1 {
@@ -78,6 +121,7 @@
                        next-level-cache = <&L2_CA57>;
                        enable-method = "psci";
                        clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>;
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                a53_0: cpu@100 {
@@ -88,6 +132,7 @@
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
                        clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                a53_1: cpu@101 {
@@ -98,6 +143,7 @@
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
                        clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                a53_2: cpu@102 {
@@ -108,6 +154,7 @@
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
                        clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                a53_3: cpu@103 {
@@ -118,6 +165,7 @@
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
                        clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>;
+                       operating-points-v2 = <&cluster1_opp>;
                };
 
                L2_CA57: cache-controller-0 {