arm64: dts: ti: k3-am65: Enable PCIe nodes at the board level

PCIe nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with a SerDes PHY.
And usually only one of the two modes can be used at a time as they
share a SerDes link.

As the PHY and mode is only known at the board integration level, these
nodes should only be enabled when provided with this information.

Disable the PCIe nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Link: https://lore.kernel.org/r/20221028142417.10642-10-afd@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index c431d67..dd7c6ae 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -632,15 +632,8 @@
        };
 };
 
-&pcie0_rc {
-       status = "disabled";
-};
-
-&pcie0_ep {
-       status = "disabled";
-};
-
 &pcie1_rc {
+       status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&minipcie_pins_default>;
 
@@ -650,10 +643,6 @@
        reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
 };
 
-&pcie1_ep {
-       status = "disabled";
-};
-
 &mailbox0_cluster0 {
        interrupts = <436>;
 

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 9cdde6e..9081c79 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -720,6 +720,7 @@
                interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
                msi-map = <0x0 &gic_its 0x0 0x10000>;
                device_type = "pci";
+               status = "disabled";
        };
 
        pcie0_ep: pcie-ep@5500000 {
@@ -733,6 +734,7 @@
                max-link-speed = <2>;
                dma-coherent;
                interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+               status = "disabled";
        };
 
        pcie1_rc: pcie@5600000 {
@@ -753,6 +755,7 @@
                interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
                msi-map = <0x0 &gic_its 0x10000 0x10000>;
                device_type = "pci";
+               status = "disabled";
        };
 
        pcie1_ep: pcie-ep@5600000 {
@@ -766,6 +769,7 @@
                max-link-speed = <2>;
                dma-coherent;
                interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
+               status = "disabled";
        };
 
        mcasp0: mcasp@2b00000 {

diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index bf6a6fe..a61060c 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -415,22 +415,6 @@
        status = "disabled";
 };
 
-&pcie0_rc {
-       status = "disabled";
-};
-
-&pcie0_ep {
-       status = "disabled";
-};
-
-&pcie1_rc {
-       status = "disabled";
-};
-
-&pcie1_ep {
-       status = "disabled";
-};
-
 &mailbox0_cluster0 {
        interrupts = <436>;