void init_program(Program *program, Stage stage, struct radv_shader_info *info,
enum chip_class chip_class, enum radeon_family family,
- ac_shader_config *config)
+ bool wgp_mode, ac_shader_config *config)
{
program->stage = stage;
program->config = config;
program->sgpr_limit = 104;
}
- program->wgp_mode = chip_class >= GFX10; /* assume WGP is used on Navi */
+ program->wgp_mode = wgp_mode;
program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
return code_size + DEBUGGER_NUM_MARKERS * 4;
}
+static bool radv_should_use_wgp_mode(const struct radv_device *device, gl_shader_stage stage,
+ const struct radv_shader_info *info)
+{
+ enum chip_class chip = device->physical_device->rad_info.chip_class;
+ switch (stage) {
+ case MESA_SHADER_COMPUTE:
+ case MESA_SHADER_TESS_CTRL:
+ return chip >= GFX10;
+ case MESA_SHADER_GEOMETRY:
+ return chip == GFX10 || (chip >= GFX10_3 && !info->is_ngg);
+ case MESA_SHADER_VERTEX:
+ case MESA_SHADER_TESS_EVAL:
+ return chip == GFX10 && info->is_ngg;
+ default:
+ return false;
+ }
+}
+
static void radv_postprocess_config(const struct radv_device *device,
const struct ac_shader_config *config_in,
const struct radv_shader_info *info,
config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
}
+ bool wgp_mode = radv_should_use_wgp_mode(device, stage, info);
+
switch (stage) {
case MESA_SHADER_TESS_EVAL:
if (info->is_ngg) {
S_00B12C_EXCP_EN(excp_en);
}
config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
- S_00B428_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
+ S_00B428_WGP_MODE(wgp_mode);
config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
break;
case MESA_SHADER_VERTEX:
break;
case MESA_SHADER_COMPUTE:
config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
- S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
+ S_00B848_WGP_MODE(wgp_mode);
config_out->rsrc2 |=
S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
* disable exactly 1 CU per SA for GS.
*/
config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
- S_00B228_WGP_MODE(pdevice->rad_info.chip_class == GFX10);
+ S_00B228_WGP_MODE(wgp_mode);
config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
S_00B22C_LDS_SIZE(config_in->lds_size) |
S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
}
config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
- S_00B228_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
+ S_00B228_WGP_MODE(wgp_mode);
config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
} else if (pdevice->rad_info.chip_class >= GFX9 &&
options.robust_buffer_access = device->robust_buffer_access;
options.robust_buffer_access2 = device->robust_buffer_access2;
options.disable_optimizations = disable_optimizations;
+ options.wgp_mode = radv_should_use_wgp_mode(device, stage, info);
return shader_variant_compile(device, module, shaders, shader_count, stage, info,
&options, false, false,
nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, NULL, "meta_trap_handler");
options.explicit_scratch_args = true;
+ options.wgp_mode = radv_should_use_wgp_mode(device, MESA_SHADER_COMPUTE, &info);
info.wave_size = 64;
shader = shader_variant_compile(device, NULL, &b.shader, 1,