[POWERPC] PPC440EP Interrupt Triggering and Level Settings

Corrected IRQ triggering and level settings according to latest revision
of the 440EP User Manual (rev 1.24 nov 16, 2007).

The incorrect settings might cause a failure of the network if both
onchip ethernet ports are under heavy load.

Signed-off-by: Wolfgang Ocker <weo@reccoware.de>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>

diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c
index 1fed663..0de9153 100644 (file)
--- a/arch/ppc/platforms/4xx/ibm440ep.c
+++ b/arch/ppc/platforms/4xx/ibm440ep.c
@@ -172,11 +172,11 @@ struct ocp_def core_ocp[] = {
 /* Polarity and triggering settings for internal interrupt sources */
 struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
        { .polarity     = 0xffbffe03,
-         .triggering   = 0xfffffe00,
+         .triggering   = 0x00000000,
          .ext_irq_mask = 0x000001fc,   /* IRQ0 - IRQ6 */
        },
-       { .polarity     = 0xffffc6ef,
-         .triggering   = 0xffffc7ff,
+       { .polarity     = 0xffffc6af,
+         .triggering   = 0x06000140,
          .ext_irq_mask = 0x00003800,   /* IRQ7 - IRQ9 */
        },
 };