This patch updates the vector long long multiply and divide tests to
supply the correct code information if power10 code generation is used.
2021-06-18 Michael Meissner <meissner@linux.ibm.com>
gcc/testsuite/
PR testsuite/100167
* gcc.target/powerpc/fold-vec-div-longlong.c: Fix expected code
generation on power10.
* gcc.target/powerpc/fold-vec-mult-longlong.c: Likewise.
{
return vec_div (x, y);
}
-/* { dg-final { scan-assembler-times {\mdivd\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mdivdu\M} 2 } } */
+
+/* { dg-final { scan-assembler-times {\mdivd\M} 2 { target { ! has_arch_pwr10 } } } } */
+/* { dg-final { scan-assembler-times {\mdivdu\M} 2 { target { ! has_arch_pwr10 } } } } */
+/* { dg-final { scan-assembler-times {\mvdivsd\M} 1 { target { has_arch_pwr10 } } } } */
+/* { dg-final { scan-assembler-times {\mvdivud\M} 1 { target { has_arch_pwr10 } } } } */
return vec_mul (x, y);
}
-/* { dg-final { scan-assembler-times "\[ \t\]mulld " 4 { target lp64 } } } */
-
+/* Power10 can generate the vmulld instruction even in 32-bit. Before power10,
+ we limit the code to lp64, since 32-bit cannot generate the mulld
+ instruction. */
+/* { dg-final { scan-assembler-times {\mmulld\M} 4 { target { lp64 && { ! has_arch_pwr10 } } } } } */
+/* { dg-final { scan-assembler-times {\mvmulld\M} 2 { target { has_arch_pwr10 } } } } */