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perf/x86/intel: Update event constraints for ICX
author
Kan Liang
<kan.liang@linux.intel.com>
Tue, 28 Sep 2021 15:19:03 +0000
(08:19 -0700)
committer
Greg Kroah-Hartman
<gregkh@linuxfoundation.org>
Wed, 6 Oct 2021 13:55:59 +0000
(15:55 +0200)
[ Upstream commit
ecc2123e09f9e71ddc6c53d71e283b8ada685fe2
]
According to the latest event list, the event encoding 0xEF is only
available on the first 4 counters. Add it into the event constraints
table.
Fixes:
6017608936c1
("perf/x86/intel: Add Icelake support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link:
https://lkml.kernel.org/r/1632842343-25862-1-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/x86/events/intel/core.c
patch
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diff --git
a/arch/x86/events/intel/core.c
b/arch/x86/events/intel/core.c
index
3b8b8ee
..
4684bf9
100644
(file)
--- a/
arch/x86/events/intel/core.c
+++ b/
arch/x86/events/intel/core.c
@@
-263,6
+263,7
@@
static struct event_constraint intel_icl_event_constraints[] = {
INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
+ INTEL_EVENT_CONSTRAINT(0xef, 0xf),
INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
EVENT_CONSTRAINT_END
};