[Arm, 2/3] Add instruction SB for AArch32

This patch is part of the patch series to add support for ARMv8.5-A
extensions.

(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)

This patch adds the instruction SB. This instruction is
retrospectively made optional for all versions of the architecture
from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a
new "+sb" for older archtectures.

*** include/ChangeLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* opcode/arm.h (ARM_EXT2_SB): New.
	(ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.

*** opcodes/ChangeLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* arm-dis.c (arm_opcodes): Add sb.
	(thumb32_opcodes): Likewise.

*** gas/ChangeLog ***

2018-10-05  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-arm.c (arm_ext_sb): New.
	(insns): Add new sb instruction.
	(arm_extensions): Add "sb".
	* doc/c-arm.texi: Document the above.
	* testsuite/gas/arm/sb-bad.d: New test.
	* testsuite/gas/arm/sb-bad.l: New test.
	* testsuite/gas/arm/sb-thumb1.d: New test.
	* testsuite/gas/arm/sb-thumb2.d: New test.
	* testsuite/gas/arm/sb.s: New test.
	* testsuite/gas/arm/sb1.d: New test.
	* testsuite/gas/arm/sb2.d: New test.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index a04d90d..9bdeb22 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,19 @@
 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 
+       * config/tc-arm.c (arm_ext_sb): New.
+       (insns): Add new sb instruction.
+       (arm_extensions): Add "sb".
+       * doc/c-arm.texi: Document the above.
+       * testsuite/gas/arm/sb-bad.d: New test.
+       * testsuite/gas/arm/sb-bad.l: New test.
+       * testsuite/gas/arm/sb-thumb1.d: New test.
+       * testsuite/gas/arm/sb-thumb2.d: New test.
+       * testsuite/gas/arm/sb.s: New test.
+       * testsuite/gas/arm/sb1.d: New test.
+       * testsuite/gas/arm/sb2.d: New test.
+
+2018-10-05  Sudakshina Das  <sudi.das@arm.com>
+
        * config/tc-arm.c (arm_archs): New entry for armv8.5-a.
        (cpu_arch_ver): Likewise.
        * doc/c-arm.texi: Add documentation for the same.

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index ef3af3a..1ecaa45 100644 (file)
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -256,6 +256,8 @@ static const arm_feature_set arm_ext_v8_2 =
   ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
 static const arm_feature_set arm_ext_v8_3 =
   ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
+static const arm_feature_set arm_ext_sb =
+  ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
 
 static const arm_feature_set arm_arch_any = ARM_ANY;
 #ifdef OBJ_ELF
@@ -21516,6 +21518,13 @@ static const struct asm_opcode insns[] =
  cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
  cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
 
+ /* ARMv8.5-A instructions.  */
+#undef  ARM_VARIANT
+#define ARM_VARIANT   & arm_ext_sb
+#undef  THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_sb
+ TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
+
  /* ARMv8-M instructions.  */
 #undef  ARM_VARIANT
 #define ARM_VARIANT NULL
@@ -26418,6 +26427,9 @@ static const struct arm_option_extension_value_table arm_extensions[] =
   ARM_EXT_OPT ("rdma",  FPU_ARCH_NEON_VFP_ARMV8_1,
                        ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
                        ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
+  ARM_EXT_OPT ("sb",   ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
+                       ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
+                       ARM_ARCH_V8A),
   ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
                        ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
                        ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),

diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 522a1db..18008c4 100644 (file)
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -189,6 +189,8 @@ The following extensions are currently supported:
 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
 architectures),
 @code{os} (Operating System for v6M architecture),
+@code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
+default from v8.5-A),
 @code{sec} (Security Extensions for v6K and v7-A architectures),
 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
 @code{virt} (Virtualization Extensions for v7-A architecture, implies

diff --git a/gas/testsuite/gas/arm/sb-bad.d b/gas/testsuite/gas/arm/sb-bad.d
new file mode 100644 (file)
index 0000000..9367dc1
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb-bad.d
@@ -0,0 +1,5 @@
+# Check sb without +sb
+#name: invalid sb instruction without +sb
+#source: sb.s
+#as: -march=armv8.2-a
+#error_output: sb-bad.l

diff --git a/gas/testsuite/gas/arm/sb-bad.l b/gas/testsuite/gas/arm/sb-bad.l
new file mode 100644 (file)
index 0000000..f27253e
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb-bad.l
@@ -0,0 +1,2 @@
+[^:]*: Assembler messages:
+[^:]*:4: Error: selected processor does not support `sb' in ARM mode

diff --git a/gas/testsuite/gas/arm/sb-thumb1.d b/gas/testsuite/gas/arm/sb-thumb1.d
new file mode 100644 (file)
index 0000000..dc3bc49
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb-thumb1.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: SB instruction (Thumb)
+#source: sb.s
+#as: -march=armv8.5-a -mthumb
+
+# Test SB Instructio
+
+.*: *file format .*arm.*
+
+Disassembly of section .text:
+.*> f3bf 8f70  sb

diff --git a/gas/testsuite/gas/arm/sb-thumb2.d b/gas/testsuite/gas/arm/sb-thumb2.d
new file mode 100644 (file)
index 0000000..892ca8f
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb-thumb2.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: SB instruction (Thumb) with +sb
+#source: sb.s
+#as: -march=armv8-a+sb -mthumb
+
+# Test SB Instructio
+
+.*: *file format .*arm.*
+
+Disassembly of section .text:
+.*> f3bf 8f70  sb

diff --git a/gas/testsuite/gas/arm/sb.s b/gas/testsuite/gas/arm/sb.s
new file mode 100644 (file)
index 0000000..9d88753
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb.s
@@ -0,0 +1,4 @@
+@ Test case to validate SB
+.section .text
+.syntax unified
+       sb

diff --git a/gas/testsuite/gas/arm/sb1.d b/gas/testsuite/gas/arm/sb1.d
new file mode 100644 (file)
index 0000000..c263d79
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb1.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: SB instruction
+#source: sb.s
+#as: -march=armv8.5-a
+
+# Test SB Instructio
+
+.*: *file format .*arm.*
+
+Disassembly of section .text:
+.*> f57ff070   sb

diff --git a/gas/testsuite/gas/arm/sb2.d b/gas/testsuite/gas/arm/sb2.d
new file mode 100644 (file)
index 0000000..cb41e09
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb2.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: SB instruction with +sb
+#source: sb.s
+#as: -march=armv8-a+sb
+
+# Test SB Instructio
+
+.*: *file format .*arm.*
+
+Disassembly of section .text:
+.*> f57ff070   sb

diff --git a/include/ChangeLog b/include/ChangeLog
index 5703b24..c78101f 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,10 @@
 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 
+       * opcode/arm.h (ARM_EXT2_SB): New.
+       (ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.
+
+2018-10-05  Sudakshina Das  <sudi.das@arm.com>
+
        * opcode/arm.h (ARM_EXT2_V8_5A): New.
        (ARM_AEXT2_V8_5A, ARM_ARCH_V8_5A): New.
 

diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index bad131e..c595799 100644 (file)
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -69,6 +69,7 @@
 #define ARM_EXT2_V8_4A  0x00000400     /* ARM V8.4A.  */
 #define ARM_EXT2_FP16_FML 0x00000800   /* ARM V8.2A FP16-FML instructions.  */
 #define ARM_EXT2_V8_5A  0x00001000     /* ARM V8.5A.  */
+#define ARM_EXT2_SB     0x00002000     /* Speculation Barrier instruction.  */
 
 /* Co-processor space extensions.  */
 #define ARM_CEXT_XSCALE   0x00000001   /* Allow MIA etc.          */
@@ -295,7 +296,8 @@
 #define ARM_ARCH_V8_4A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_4A,     \
                                     CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \
                                     | FPU_NEON_EXT_DOTPROD)
-#define ARM_ARCH_V8_5A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_5A,     \
+#define ARM_ARCH_V8_5A ARM_FEATURE (ARM_AEXT_V8A,      \
+                                    ARM_AEXT2_V8_5A | ARM_EXT2_SB,     \
                                     CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA \
                                     | FPU_NEON_EXT_DOTPROD)
 #define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0eda28d..b66a46e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2018-10-05  Sudakshina Das  <sudi.das@arm.com>
+
+       * arm-dis.c (arm_opcodes): Add sb.
+       (thumb32_opcodes): Likewise.
+
 2018-10-05  Richard Henderson  <rth@twiddle.net>
            Stafford Horne  <shorne@gmail.com>
 

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index cb2de1b..f22a78f 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1906,6 +1906,9 @@ static const struct opcode32 arm_opcodes[] =
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
 
+  /* ARMv8.5-A instructions.  */
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf57ff070, 0xffffffff, "sb"},
+
   /* ARM V6K NOP hints.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
     0x0320f001, 0x0fffffff, "yield%c"},
@@ -2829,6 +2832,9 @@ static const struct opcode32 thumb32_opcodes[] =
   /* Security extension instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
 
+  /* ARMv8.5-A instructions.  */
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB), 0xf3bf8f70, 0xffffffff, "sb"},
+
   /* Instructions defined in the basic V6T2 set.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},