vpp: sr: disable core0 and core1 scaler latch [1/1]
authorBrian Zhu <brian.zhu@amlogic.com>
Wed, 26 Dec 2018 10:55:36 +0000 (18:55 +0800)
committerJianxin Pan <jianxin.pan@amlogic.com>
Thu, 27 Dec 2018 01:40:48 +0000 (17:40 -0800)
PD#SWPL-3144

Problem:
The latch function cause the super scaler size asynchronous

Solution:
Disable sr core0 and core1 scaler latch

Verify:
T962x2 x301 board test pass

Change-Id: Iecbcc3e0c751093b6515f7b46973eca2157cd349
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
drivers/amlogic/media/video_sink/video.c
include/linux/amlogic/media/registers/regs/vpp_regs.h

index 69eabce..5ea36e8 100644 (file)
@@ -10353,10 +10353,19 @@ static int __init video_early_init(void)
                        DMC_AM0_CHAN_CTRL,
                        0x8ff403cf);
 
-       /* force bypass dolby for TL1. There is no dolby function */
-       if (is_meson_tl1_cpu())
+       if (is_meson_tl1_cpu()) {
+               /* force bypass dolby for TL1, no dolby function */
                WRITE_VCBUS_REG_BITS(
                        DOLBY_PATH_CTRL, 0xf, 0, 6);
+               /* disable latch for sr core0/1 scaler */
+               WRITE_VCBUS_REG_BITS(
+                       SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1);
+               WRITE_VCBUS_REG_BITS(
+                       SRSHARP1_SHARP_SYNC_CTRL, 1, 8, 1);
+       }
+       if (is_meson_g12b_cpu())
+               WRITE_VCBUS_REG_BITS(
+                       SRSHARP0_SHARP_SYNC_CTRL, 1, 8, 1);
        return 0;
 }
 
index c82b4ba..7daba09 100644 (file)
 #define OSD1_BLEND_SRC_CTRL 0x1dfd
 #define OSD2_BLEND_SRC_CTRL 0x1dfe
 
+/* after g12b */
+#define SRSHARP0_SHARP_SYNC_CTRL 0x3eb0
+#define SRSHARP1_SHARP_SYNC_CTRL 0x3fb0
 #endif