#include <asm/hpet.h>
#include <asm/io.h>
-#define HPET_MASK 0xFFFFFFFF
+#define HPET_MASK CLOCKSOURCE_MASK(32)
#define HPET_SHIFT 22
/* FSEC = 10^-15 NSEC = 10^-9 */
.name = "hpet",
.rating = 250,
.read = read_hpet,
- .mask = (cycle_t)HPET_MASK,
+ .mask = HPET_MASK,
.mult = 0, /* set below */
.shift = HPET_SHIFT,
.is_continuous = 1,
.name = "pit",
.rating = 110,
.read = pit_read,
- .mask = (cycle_t)-1,
+ .mask = CLOCKSOURCE_MASK(64),
.mult = 0,
.shift = 20,
};
.name = "tsc",
.rating = 300,
.read = read_tsc,
- .mask = (cycle_t)-1,
+ .mask = CLOCKSOURCE_MASK(64),
.mult = 0, /* to be set */
.shift = 22,
.update_callback = tsc_update_callback,
*/
u32 pmtmr_ioport __read_mostly;
-#define ACPI_PM_MASK 0xFFFFFF /* limit it to 24 bits */
+#define ACPI_PM_MASK CLOCKSOURCE_MASK(24) /* limit it to 24 bits */
static inline u32 read_pmtmr(void)
{
#define CYCLONE_MPCS_OFFSET 0x51A8 /* offset to select register */
#define CYCLONE_MPMC_OFFSET 0x51D0 /* offset to count register */
#define CYCLONE_TIMER_FREQ 99780000 /* 100Mhz, but not really */
-#define CYCLONE_TIMER_MASK 0xFFFFFFFF /* 32 bit mask */
+#define CYCLONE_TIMER_MASK CLOCKSOURCE_MASK(32) /* 32 bit mask */
int use_cyclone = 0;
static void __iomem *cyclone_ptr;
.name = "cyclone",
.rating = 250,
.read = read_cyclone,
- .mask = (cycle_t)CYCLONE_TIMER_MASK,
+ .mask = CYCLONE_TIMER_MASK,
.mult = 10,
.shift = 0,
.is_continuous = 1,
u64 interval_snsecs;
};
+/* simplify initialization of mask field */
+#define CLOCKSOURCE_MASK(bits) (cycle_t)(bits<64 ? ((1ULL<<bits)-1) : -1)
/**
* clocksource_khz2mult - calculates mult from khz and shift