PCI: dwc: Introduce generic controller capabilities interface

Since in addition to the already available iATU unrolled mapping we are
about to add a few more DW PCIe platform-specific capabilities (CDM-check
and generic clocks/resets resources) let's add a generic interface to set
and get the flags indicating their availability. The new interface shall
improve maintainability of the platform-specific code.

Link: https://lore.kernel.org/r/20221113191301.5526-17-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 7f1fb76..b9cc4b0 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -211,7 +211,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
 static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir,
                                               u32 index)
 {
-       if (pci->iatu_unroll_enabled)
+       if (dw_pcie_cap_is(pci, IATU_UNROLL))
                return pci->atu_base + PCIE_ATU_UNROLL_BASE(dir, index);
 
        dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, dir | index);
@@ -591,7 +591,7 @@ static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
        u32 val, min, dir;
        u64 max;
 
-       if (pci->iatu_unroll_enabled) {
+       if (dw_pcie_cap_is(pci, IATU_UNROLL)) {
                max_region = min((int)pci->atu_size / 512, 256);
        } else {
                dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF);
@@ -641,8 +641,9 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
 {
        struct platform_device *pdev = to_platform_device(pci->dev);
 
-       pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
-       if (pci->iatu_unroll_enabled) {
+       if (dw_pcie_iatu_unroll_enabled(pci)) {
+               dw_pcie_cap_set(pci, IATU_UNROLL);
+
                if (!pci->atu_base) {
                        struct resource *res =
                                platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
@@ -664,7 +665,7 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
 
        dw_pcie_iatu_detect_regions(pci);
 
-       dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
+       dev_info(pci->dev, "iATU unroll: %s\n", dw_pcie_cap_is(pci, IATU_UNROLL) ?
                "enabled" : "disabled");
 
        dev_info(pci->dev, "iATU regions: %u ob, %u ib, align %uK, limit %lluG\n",

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 37801bb..c6dddac 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -12,6 +12,7 @@
 #define _PCIE_DESIGNWARE_H
 
 #include <linux/bitfield.h>
+#include <linux/bitops.h>
 #include <linux/dma-mapping.h>
 #include <linux/irq.h>
 #include <linux/msi.h>
@@ -43,6 +44,15 @@
        (__dw_pcie_ver_cmp(_pci, _ver, ==) && \
         __dw_pcie_ver_cmp(_pci, TYPE_ ## _type, >=))
 
+/* DWC PCIe controller capabilities */
+#define DW_PCIE_CAP_IATU_UNROLL                1
+
+#define dw_pcie_cap_is(_pci, _cap) \
+       test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
+
+#define dw_pcie_cap_set(_pci, _cap) \
+       set_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
+
 /* Parameters for the waiting for link up routine */
 #define LINK_WAIT_MAX_RETRIES          10
 #define LINK_WAIT_USLEEP_MIN           90000
@@ -317,10 +327,10 @@ struct dw_pcie {
        const struct dw_pcie_ops *ops;
        u32                     version;
        u32                     type;
+       unsigned long           caps;
        int                     num_lanes;
        int                     link_gen;
        u8                      n_fts[2];
-       bool                    iatu_unroll_enabled: 1;
 };
 
 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)