if (offset || /* Non-zero planes ignore metadata. */
size_metadata < 10 * 4 || /* at least 2(header) + 8(desc) dwords */
- metadata[0] == 0 || /* invalid version number */
+ metadata[0] == 0 || /* invalid version number (1 and 2 layouts are compatible) */
metadata[1] != ac_get_umd_metadata_word1(info)) /* invalid PCI ID */ {
/* Disable DCC because it might not be enabled. */
ac_surface_zero_dcc_fields(surf);
void ac_surface_compute_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf,
unsigned num_mipmap_levels, uint32_t desc[8],
- unsigned *size_metadata, uint32_t metadata[64])
+ unsigned *size_metadata, uint32_t metadata[64],
+ bool include_tool_md)
{
/* Clear the base address and set the relative DCC offset. */
desc[0] = 0;
assert(0);
}
- /* Metadata image format format version 1:
- * [0] = 1 (metadata format identifier)
+ /* Metadata image format format version 1 and 2. Version 2 uses the same layout as
+ * version 1 with some additional fields (used if include_tool_md=true).
+ * [0] = metadata_format_identifier
* [1] = (VENDOR_ID << 16) | PCI_ID
* [2:9] = image descriptor for the whole resource
* [2] is always 0, because the base address is cleared
* [9] is the DCC offset bits [39:8] from the beginning of
* the buffer
- * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
+ * gfx8-: [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level (gfx8-)
+ * ---- The data below is only set in version=2.
+ * It shouldn't be used by the driver as it's only present to help
+ * tools (eg: umr) that would want to access this buffer.
+ * gfx9+ if valid modifier: [10:11] = modifier
+ * [12:12+3*nplane] = [offset, stride]
+ * else: [10]: stride
*/
-
- metadata[0] = 1; /* metadata image format version 1 */
+ metadata[0] = include_tool_md ? 2 : 1; /* metadata image format version */
/* Tiling modes are ambiguous without a PCI ID. */
metadata[1] = ac_get_umd_metadata_word1(info);
metadata[10 + i] = surf->u.legacy.level[i].offset_256B;
*size_metadata += num_mipmap_levels * 4;
+ } else if (include_tool_md) {
+ if (surf->modifier != DRM_FORMAT_MOD_INVALID) {
+ /* Modifier */
+ metadata[10] = surf->modifier;
+ metadata[11] = surf->modifier >> 32;
+ /* Num planes */
+ int nplanes = ac_surface_get_nplanes(surf);
+ metadata[12] = nplanes;
+ int ndw = 13;
+ for (int i = 0; i < nplanes; i++) {
+ metadata[ndw++] = ac_surface_get_plane_offset(info->gfx_level,
+ surf, i, 0);
+ metadata[ndw++] = ac_surface_get_plane_stride(info->gfx_level,
+ surf, i, 0);
+ }
+ *size_metadata = ndw * 4;
+ } else {
+ metadata[10] = ac_surface_get_plane_stride(info->gfx_level,
+ surf, 0, 0);
+ *size_metadata = 11 * 4;
+ }
}
}
unsigned size_metadata, const uint32_t metadata[64]);
void ac_surface_compute_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf,
unsigned num_mipmap_levels, uint32_t desc[8],
- unsigned *size_metadata, uint32_t metadata[64]);
+ unsigned *size_metadata, uint32_t metadata[64],
+ bool include_tool_md);
bool ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf,
unsigned num_mipmap_levels, uint64_t offset, unsigned pitch);