hdmitx: fix no display under frac_mode

PD#166241: hdmitx: fix no display under frac_mode

1.update pll parameters
2.4k60hz444/rgb8bit doesn't frac_mode

Change-Id: I45c8bade4cd8f83a7b4d36aadbdbbaa9dfca32f1
Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c
index f36d837e71b8da6bc0c0302162675f01211104c9..01f3d441110076d73a9d8596849909f8b83d321b 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c
@@ -333,6 +333,7 @@ static struct frac_rate_table fr_tab[] = {
 static void recalc_vinfo_sync_duration(struct vinfo_s *info, unsigned int frac)
 {
        struct frac_rate_table *fr = &fr_tab[0];
+       struct hdmitx_dev *hdev = &hdmitx_device;
 
        pr_info(SYS "recalc before %s %d %d\n", info->name,
                info->sync_duration_num, info->sync_duration_den);
@@ -346,6 +347,19 @@ static void recalc_vinfo_sync_duration(struct vinfo_s *info, unsigned int frac)
                                info->sync_duration_num = fr->sync_num_int;
                                info->sync_duration_den = fr->sync_den_int;
                        }
+
+                       if (hdev->chip_type == MESON_CPU_ID_G12A)
+                               if ((hdev->cur_VIC ==
+                                               HDMI_3840x2160p60_16x9) ||
+                                       (hdev->cur_VIC ==
+                                               HDMI_4096x2160p60_256x135))
+                                       if (hdev->para->cs !=
+                                               COLORSPACE_YUV420) {
+                                               info->sync_duration_num
+                                                       = fr->sync_num_int;
+                                               info->sync_duration_den
+                                                       = fr->sync_den_int;
+                                       }
                        break;
                }
                fr++;

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
index 445ce55e1b94e798dfa723ee5a8fc2d2f9185598..2fd19954dd9d38c6de1c64b2413e6c4188419410 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c
@@ -999,9 +999,15 @@ static void hdmitx_check_frac_rate(struct hdmitx_dev *hdev)
 
        frac_rate = hdev->frac_rate_policy;
        para = hdmi_get_fmt_paras(vic);
-       if (para && (para->name) && likely_frac_rate_mode(para->name))
-               ;
-       else {
+       if (para && (para->name) && likely_frac_rate_mode(para->name)) {
+               if (hdev->chip_type == MESON_CPU_ID_G12A)
+                       if ((vic == HDMI_3840x2160p60_16x9) ||
+                               (vic == HDMI_4096x2160p60_256x135))
+                               if (para->cs != COLORSPACE_YUV420) {
+                                       pr_info("g12a 6GHz doesn't have frac_rate\n");
+                                       frac_rate = 0;
+                               }
+       } else {
                pr_info("%s doesn't have frac_rate\n", para->name);
                frac_rate = 0;
        }

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
index d7a24b5f0a34f0b2f3aaa4d3f4f6df95996aa4a4..19186bb45b0587e3f853a7699df10223a4e2622a 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_g12a.c
@@ -94,9 +94,15 @@ static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val)
        hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff));
        hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2);
        hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val);
-       hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
-       hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a68dc00);
-       hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+       if (frac_val == 0x8148) {
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x44331290);
+       } else {
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a68dc00);
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+       }
        hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
        hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540000);
        hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
@@ -149,13 +155,14 @@ static bool set_hpll_hclk_v3(unsigned int m, unsigned int frac_val)
 
 void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
 {
+
        switch (clk) {
        case 5940000:
-               if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8168 : 0x10000))
+               if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000))
                        break;
                else if (set_hpll_hclk_v2(0x7b, frac_rate ? 0x140b4 : 0x18000))
                        break;
-               else if (set_hpll_hclk_v3(0xf7, frac_rate ? 0x8168 : 0x10000))
+               else if (set_hpll_hclk_v3(0xf7, frac_rate ? 0x8148 : 0x10000))
                        break;
                else
                        break;
@@ -182,10 +189,10 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
                else
                        hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00014000);
                hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
-               hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
-               hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
-               hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
-               hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
                hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
                WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
                pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
@@ -212,10 +219,10 @@ void set_g12a_hpll_clk_out(unsigned int frac_rate, unsigned int clk)
                else
                        hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000);
                hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
-               hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
-               hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
-               hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
-               hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+               hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
                hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
                WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
                pr_info("HPLL: 0x%x\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));