Kernel "cleanfile" script run.
static int drm_agp_populate(struct drm_ttm_backend *backend, unsigned long num_pages,
struct page **pages) {
- struct drm_agp_ttm_backend *agp_be =
+ struct drm_agp_ttm_backend *agp_be =
container_of(backend, struct drm_agp_ttm_backend, backend);
struct page **cur_page, **last_page = pages + num_pages;
DRM_AGP_MEM *mem;
static int drm_agp_unbind_ttm(struct drm_ttm_backend *backend) {
- struct drm_agp_ttm_backend *agp_be =
+ struct drm_agp_ttm_backend *agp_be =
container_of(backend, struct drm_agp_ttm_backend, backend);
DRM_DEBUG("drm_agp_unbind_ttm\n");
static void drm_agp_clear_ttm(struct drm_ttm_backend *backend) {
- struct drm_agp_ttm_backend *agp_be =
+ struct drm_agp_ttm_backend *agp_be =
container_of(backend, struct drm_agp_ttm_backend, backend);
DRM_AGP_MEM *mem = agp_be->mem;
}
}
-static struct drm_ttm_backend_func agp_ttm_backend =
+static struct drm_ttm_backend_func agp_ttm_backend =
{
.needs_ub_cache_adjust = drm_agp_needs_unbind_cache_adjust,
.populate = drm_agp_populate,
return NULL;
}
-
+
agp_be = drm_ctl_calloc(1, sizeof(*agp_be), DRM_MEM_TTM);
if (!agp_be)
return NULL;
int drm_bo_handle_validate(struct drm_file * file_priv, uint32_t handle,
uint32_t fence_class,
- uint64_t flags, uint64_t mask,
+ uint64_t flags, uint64_t mask,
uint32_t hint,
int use_old_fence_class,
struct drm_bo_info_rep * rep,
bo = drm_lookup_buffer_object(file_priv, handle, 1);
mutex_unlock(&dev->struct_mutex);
- if (!bo)
+ if (!bo)
return -EINVAL;
if (use_old_fence_class)
* Only allow creator to change shared buffer mask.
*/
- if (bo->base.owner != file_priv)
+ if (bo->base.owner != file_priv)
mask &= ~(DRM_BO_FLAG_NO_EVICT | DRM_BO_FLAG_NO_MOVE);
-
+
ret = drm_bo_do_validate(bo, flags, mask, hint, fence_class,
no_wait, rep);
req->buffer_start, &entry);
if (ret)
goto out;
-
+
ret = drm_bo_add_user_object(file_priv, entry,
req->mask & DRM_BO_FLAG_SHAREABLE);
if (ret) {
drm_bo_usage_deref_unlocked(&entry);
goto out;
}
-
+
mutex_lock(&entry->mutex);
drm_bo_fill_rep_arg(entry, rep);
mutex_unlock(&entry->mutex);
return ret;
}
-int drm_bo_setstatus_ioctl(struct drm_device *dev,
+int drm_bo_setstatus_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv)
{
struct drm_bo_map_wait_idle_arg *arg = data;
drm_buffer_type, &uo);
if (ret)
return ret;
-
+
ret = drm_bo_handle_info(file_priv, req->handle, rep);
if (ret)
return ret;
/*
* This function is intended to be called on drm driver unload.
* If you decide to call it from lastclose, you must protect the call
- * from a potentially racing drm_bo_driver_init in firstopen.
+ * from a potentially racing drm_bo_driver_init in firstopen.
* (This may happen on X server restart).
*/
/*
* This function is intended to be called on drm driver load.
* If you decide to call it from firstopen, you must protect the call
- * from a potentially racing drm_bo_driver_finish in lastclose.
+ * from a potentially racing drm_bo_driver_finish in lastclose.
* (This may happen on X server restart).
*/
DRM_ERROR("Lock flag DRM_BO_LOCK_IGNORE_NO_EVICT not supported yet.\n");
return -EINVAL;
}
-
+
if (arg->lock_flags & DRM_BO_LOCK_UNLOCK_BM) {
ret = drm_bo_write_lock(&dev->bm.bm_lock, file_priv);
if (ret)
return ret;
}
-
+
mutex_lock(&dev->struct_mutex);
ret = drm_bo_lock_mm(dev, arg->mem_type);
mutex_unlock(&dev->struct_mutex);
return 0;
}
-int drm_mm_unlock_ioctl(struct drm_device *dev,
- void *data,
+int drm_mm_unlock_ioctl(struct drm_device *dev,
+ void *data,
struct drm_file *file_priv)
{
struct drm_mm_type_arg *arg = data;
if (ret)
return ret;
}
-
+
return 0;
}
return 0;
}
-int drm_bo_version_ioctl(struct drm_device *dev, void *data,
+int drm_bo_version_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
struct drm_bo_version_arg *arg = (struct drm_bo_version_arg *)data;
-
+
arg->major = DRM_BO_INIT_MAJOR;
arg->minor = DRM_BO_INIT_MINOR;
arg->patchlevel = DRM_BO_INIT_PATCH;
/*
* This file implements a simple replacement for the buffer manager use
* of the heavyweight hardware lock.
- * The lock is a read-write lock. Taking it in read mode is fast, and
+ * The lock is a read-write lock. Taking it in read mode is fast, and
* intended for in-kernel use only.
* Taking it in write mode is slow.
*
- * The write mode is used only when there is a need to block all
- * user-space processes from allocating a
+ * The write mode is used only when there is a need to block all
+ * user-space processes from allocating a
* new memory area.
* Typical use in write mode is X server VT switching, and it's allowed
* to leave kernel space with the write lock held. If a user-space process
* dies while having the write-lock, it will be released during the file
* descriptor release.
*
- * The read lock is typically placed at the start of an IOCTL- or
+ * The read lock is typically placed at the start of an IOCTL- or
* user-space callable function that may end up allocating a memory area.
* This includes setstatus, super-ioctls and no_pfn; the latter may move
* unmappable regions to mappable. It's a bug to leave kernel space with the
* latency. The locking functions will return -EAGAIN if interrupted by a
* signal.
*
- * Locking order: The lock should be taken BEFORE any kernel mutexes
+ * Locking order: The lock should be taken BEFORE any kernel mutexes
* or spinlocks.
*/
/*
* Add a dummy user-object, the destructor of which will
- * make sure the lock is released if the client dies
+ * make sure the lock is released if the client dies
* while holding it.
*/
/**************************************************************************
- *
+ *
* Copyright (c) 2007 Tungsten Graphics, Inc., Cedar Park, TX., USA
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
*
* \param bo The buffer object.
* \return Failure indication.
- *
+ *
* Returns -EINVAL if the buffer object is currently not mappable.
* Returns -ENOMEM if the ioremap operation failed.
* Otherwise returns zero.
- *
+ *
* After a successfull call, bo->iomap contains the virtual address, or NULL
- * if the buffer object content is not accessible through PCI space.
+ * if the buffer object content is not accessible through PCI space.
* Call bo->mutex locked.
*/
#ifdef DRM_ODD_MM_COMPAT
/*
* In this mode, we don't allow pipelining a copy blit,
- * since the buffer will be accessible from user space
+ * since the buffer will be accessible from user space
* the moment we return and rebuild the page tables.
*
* With normal vm operation, page tables are rebuilt
- * on demand using fault(), which waits for buffer idle.
+ * on demand using fault(), which waits for buffer idle.
*/
if (1)
#else
struct drm_map_list *entry;
list_for_each_entry(entry, &dev->maplist, head) {
if (entry->map && map->type == entry->map->type &&
- ((entry->map->offset == map->offset) ||
+ ((entry->map->offset == map->offset) ||
(map->type == _DRM_SHM && map->flags==_DRM_CONTAINS_LOCK))) {
return entry;
}
int ret;
hash->key = user_token >> PAGE_SHIFT;
ret = drm_ht_insert_item(&dev->map_hash, hash);
- if (ret != -EINVAL)
+ if (ret != -EINVAL)
return ret;
}
- return drm_ht_just_insert_please(&dev->map_hash, hash,
+ return drm_ht_just_insert_please(&dev->map_hash, hash,
user_token, 32 - PAGE_SHIFT - 3,
0, DRM_MAP_HASH_OFFSET >> PAGE_SHIFT);
}
/* Assign a 32-bit handle */
- user_token = (map->type == _DRM_SHM) ? (unsigned long) map->handle :
+ user_token = (map->type == _DRM_SHM) ? (unsigned long) map->handle :
map->offset;
ret = drm_map_handle(dev, &list->hash, user_token, 0);
list_for_each_entry_safe(r_list, list_t, &dev->maplist, head) {
if (r_list->map == map) {
list_del(&r_list->head);
- drm_ht_remove_key(&dev->map_hash,
+ drm_ht_remove_key(&dev->map_hash,
r_list->user_token >> PAGE_SHIFT);
drm_free(r_list, sizeof(*r_list), DRM_MEM_MAPS);
found = 1;
page_count = 0;
while (entry->buf_count < count) {
-
+
dmah = drm_pci_alloc(dev, PAGE_SIZE << page_order, 0x1000, 0xfffffffful);
-
+
if (!dmah) {
/* Set count correctly so we free the proper amount. */
entry->buf_count = count;
return order;
}
EXPORT_SYMBOL(drm_order);
-
-
/**************************************************************************
- *
+ *
* This kernel module is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
+ *
**************************************************************************/
/*
* This code provides access to unexported mm kernel features. It is necessary
* directly.
*
* Authors: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
- * Linux kernel mm subsystem authors.
+ * Linux kernel mm subsystem authors.
* (Most code taken from there).
*/
* performance reasons */
return i;
}
-#endif
+#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19))
/*
* vm code for kernels below 2.6.15 in which version a major vm write
- * occured. This implement a simple straightforward
+ * occured. This implement a simple straightforward
* version similar to what's going to be
* in kernel 2.6.19+
* Kernels below 2.6.15 use nopage whereas 2.6.19 and upwards use
* nopfn.
- */
+ */
static struct {
spinlock_t lock;
struct page *dummy_page;
atomic_t present;
-} drm_np_retry =
+} drm_np_retry =
{SPIN_LOCK_UNLOCKED, NOPAGE_OOM, ATOMIC_INIT(0)};
-static struct page *drm_bo_vm_fault(struct vm_area_struct *vma,
+static struct page *drm_bo_vm_fault(struct vm_area_struct *vma,
struct fault_data *data);
}
struct page *drm_bo_vm_nopage(struct vm_area_struct *vma,
- unsigned long address,
+ unsigned long address,
int *type)
{
struct fault_data data;
struct drm_buffer_object *bo = (struct drm_buffer_object *) vma->vm_private_data;
unsigned long page_offset;
struct page *page = NULL;
- struct drm_ttm *ttm;
+ struct drm_ttm *ttm;
struct drm_device *dev;
unsigned long pfn;
int err;
unsigned long bus_base;
unsigned long bus_offset;
unsigned long bus_size;
-
+
dev = bo->dev;
while(drm_bo_read_lock(&dev->bm.bm_lock));
err = drm_bo_wait(bo, 0, 1, 0);
if (err) {
- data->type = (err == -EAGAIN) ?
+ data->type = (err == -EAGAIN) ?
VM_FAULT_MINOR : VM_FAULT_SIGBUS;
goto out_unlock;
}
-
-
+
+
/*
* If buffer happens to be in a non-mappable location,
* move it to a mappable.
}
dev = bo->dev;
- err = drm_bo_pci_offset(dev, &bo->mem, &bus_base, &bus_offset,
+ err = drm_bo_pci_offset(dev, &bo->mem, &bus_base, &bus_offset,
&bus_size);
if (err) {
err = vm_insert_pfn(vma, address, pfn);
if (!err || err == -EBUSY)
- data->type = VM_FAULT_MINOR;
+ data->type = VM_FAULT_MINOR;
else
data->type = VM_FAULT_OOM;
out_unlock:
* VM compatibility code for 2.6.15-2.6.18. This code implements a complicated
* workaround for a single BUG statement in do_no_page in these versions. The
* tricky thing is that we need to take the mmap_sem in exclusive mode for _all_
- * vmas mapping the ttm, before dev->struct_mutex is taken. The way we do this is to
+ * vmas mapping the ttm, before dev->struct_mutex is taken. The way we do this is to
* check first take the dev->struct_mutex, and then trylock all mmap_sems. If this
* fails for a single mmap_sem, we have to release all sems and the dev->struct_mutex,
* release the cpu and retry. We also need to keep track of all vmas mapping the ttm.
struct page *drm_bo_vm_nopage(struct vm_area_struct *vma,
- unsigned long address,
+ unsigned long address,
int *type)
{
struct drm_buffer_object *bo = (struct drm_buffer_object *) vma->vm_private_data;
unsigned long page_offset;
struct page *page;
- struct drm_ttm *ttm;
+ struct drm_ttm *ttm;
struct drm_device *dev;
mutex_lock(&bo->mutex);
page = NOPAGE_SIGBUS;
goto out_unlock;
}
-
+
dev = bo->dev;
if (drm_mem_reg_is_pci(dev, &bo->mem)) {
unsigned long bus_base;
unsigned long bus_offset;
unsigned long bus_size;
-
- ret = drm_bo_pci_offset(bo->dev, &bo->mem, &bus_base,
+
+ ret = drm_bo_pci_offset(bo->dev, &bo->mem, &bus_base,
&bus_offset, &bus_size);
BUG_ON(ret);
return ret;
}
-
+
int drm_bo_add_vma(struct drm_buffer_object * bo, struct vm_area_struct *vma)
{
{
p_mm_entry_t *entry;
int lock_ok = 1;
-
+
list_for_each_entry(entry, &bo->p_mm_list, head) {
BUG_ON(entry->locked);
if (!down_write_trylock(&entry->mm->mmap_sem)) {
return 0;
list_for_each_entry(entry, &bo->p_mm_list, head) {
- if (!entry->locked)
+ if (!entry->locked)
break;
up_write(&entry->mm->mmap_sem);
entry->locked = 0;
void drm_bo_unlock_kmm(struct drm_buffer_object * bo)
{
p_mm_entry_t *entry;
-
+
list_for_each_entry(entry, &bo->p_mm_list, head) {
BUG_ON(!entry->locked);
up_write(&entry->mm->mmap_sem);
}
}
-int drm_bo_remap_bound(struct drm_buffer_object *bo)
+int drm_bo_remap_bound(struct drm_buffer_object *bo)
{
vma_entry_t *v_entry;
int ret = 0;
vma_entry_t *v_entry;
list_for_each_entry(v_entry, &bo->vma_list, head) {
- v_entry->vma->vm_flags &= ~VM_PFNMAP;
+ v_entry->vma->vm_flags &= ~VM_PFNMAP;
}
-}
+}
#endif
#define __user
#endif
-#if !defined(__put_page)
+#if !defined(__put_page)
#define __put_page(p) atomic_dec(&(p)->count)
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10)
static inline int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t pgprot)
{
- return remap_page_range(vma, from,
+ return remap_page_range(vma, from,
pfn << PAGE_SHIFT,
size,
pgprot);
/*
- * Flush relevant caches and clear a VMA structure so that page references
+ * Flush relevant caches and clear a VMA structure so that page references
* will cause a page fault. Don't flush tlbs.
*/
unsigned long addr, unsigned long end);
/*
- * Return the PTE protection map entries for the VMA flags given by
+ * Return the PTE protection map entries for the VMA flags given by
* flags. This is a functional interface to the kernel's protection map.
*/
#ifndef DRM_FULL_MM_COMPAT
/*
- * For now, just return a dummy page that we've allocated out of
+ * For now, just return a dummy page that we've allocated out of
* static space. The page will be put by do_nopage() since we've already
* filled out the pte.
*/
unsigned long address;
pgoff_t pgoff;
unsigned int flags;
-
+
int type;
};
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19))
extern struct page *drm_bo_vm_nopage(struct vm_area_struct *vma,
- unsigned long address,
+ unsigned long address,
int *type);
#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,19)) && \
!defined(DRM_FULL_MM_COMPAT)
/*
- * Add a vma to the ttm vma list, and the
+ * Add a vma to the ttm vma list, and the
* process mm pointer to the ttm mm list. Needs the ttm mutex.
*/
-extern int drm_bo_add_vma(struct drm_buffer_object * bo,
+extern int drm_bo_add_vma(struct drm_buffer_object * bo,
struct vm_area_struct *vma);
/*
* Delete a vma and the corresponding mm pointer from the
* ttm lists. Needs the ttm mutex.
*/
-extern void drm_bo_delete_vma(struct drm_buffer_object * bo,
+extern void drm_bo_delete_vma(struct drm_buffer_object * bo,
struct vm_area_struct *vma);
/*
* Attempts to lock all relevant mmap_sems for a ttm, while
- * not releasing the ttm mutex. May return -EAGAIN to avoid
+ * not releasing the ttm mutex. May return -EAGAIN to avoid
* deadlocks. In that case the caller shall release the ttm mutex,
* schedule() and try again.
*/
extern void drm_bo_finish_unmap(struct drm_buffer_object *bo);
/*
- * Remap all vmas of this ttm using io_remap_pfn_range. We cannot
+ * Remap all vmas of this ttm using io_remap_pfn_range. We cannot
* fault these pfns in, because the first one will set the vma VM_PFNMAP
* flag, which will make the next fault bug in do_nopage(). The function
* releases the mmap_sems for this ttm.
mutex_unlock(&dev->struct_mutex);
goto again;
}
-
+
mutex_unlock(&dev->struct_mutex);
return new_id;
}
request->handle = NULL;
list_for_each_entry(_entry, &dev->maplist, head) {
if (_entry->map == map) {
- request->handle =
+ request->handle =
(void *)(unsigned long)_entry->user_token;
break;
}
DRM_IOCTL_DEF(DRM_IOCTL_UPDATE_DRAW, drm_update_drawable_info, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF(DRM_IOCTL_MM_INIT, drm_mm_init_ioctl,
+ DRM_IOCTL_DEF(DRM_IOCTL_MM_INIT, drm_mm_init_ioctl,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF(DRM_IOCTL_MM_TAKEDOWN, drm_mm_takedown_ioctl,
+ DRM_IOCTL_DEF(DRM_IOCTL_MM_TAKEDOWN, drm_mm_takedown_ioctl,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF(DRM_IOCTL_MM_LOCK, drm_mm_lock_ioctl,
+ DRM_IOCTL_DEF(DRM_IOCTL_MM_LOCK, drm_mm_lock_ioctl,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF(DRM_IOCTL_MM_UNLOCK, drm_mm_unlock_ioctl,
+ DRM_IOCTL_DEF(DRM_IOCTL_MM_UNLOCK, drm_mm_unlock_ioctl,
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_IOCTL_FENCE_CREATE, drm_fence_create_ioctl, DRM_AUTH),
list_del(&vma->head);
drm_ctl_free(vma, sizeof(*vma), DRM_MEM_VMAS);
}
-
+
list_for_each_entry_safe(r_list, list_t, &dev->maplist, head) {
drm_rmmap_locked(dev, r_list->map);
r_list = NULL;
pci_get_subsys(pid->vendor, pid->device, pid->subvendor,
pid->subdevice, pdev))) {
/* Are there device class requirements? */
- if ((pid->class != 0)
+ if ((pid->class != 0)
&& ((pdev->class & pid->class_mask) != pid->class)) {
continue;
}
pid->subvendor, pid->subdevice,
pdev))) {
/* Are there device class requirements? */
- if ((pid->class != 0)
+ if ((pid->class != 0)
&& ((pdev->class & pid->class_mask) != pid->class)) {
continue;
}
unsigned long max_memctl_mem;
si_meminfo(&si);
-
+
/*
* AGP only allows low / DMA32 memory ATM.
*/
avail_memctl_mem = si.totalram - si.totalhigh;
- /*
- * Avoid overflows
+ /*
+ * Avoid overflows
*/
max_memctl_mem = 1UL << (32 - PAGE_SHIFT);
- max_memctl_mem = (max_memctl_mem / si.mem_unit) * PAGE_SIZE;
+ max_memctl_mem = (max_memctl_mem / si.mem_unit) * PAGE_SIZE;
if (avail_memctl_mem >= max_memctl_mem)
avail_memctl_mem = max_memctl_mem;
list_for_each_entry(fence, head, ring) {
if (&fence->ring == &fc->ring)
break;
- diff = (fc->last_exe_flush - fence->sequence) &
+ diff = (fc->last_exe_flush - fence->sequence) &
driver->sequence_mask;
if (diff > driver->wrap_diff)
break;
write_lock_irqsave(&fm->lock, flags);
INIT_LIST_HEAD(&fence->ring);
- /*
+ /*
* Avoid hitting BUG() for kernel-only fence objects.
*/
drm_fence_usage_deref_unlocked(&fence);
return ret;
}
-
+
/*
* usage > 0. No need to lock dev->struct_mutex;
*/
return 0;
}
EXPORT_SYMBOL(drm_poll);
-
}
/*
- * Just insert an item and return any "bits" bit key that hasn't been
+ * Just insert an item and return any "bits" bit key that hasn't been
* used before.
*/
int drm_ht_just_insert_please(struct drm_open_hash * ht, struct drm_hash_item * item,
entry = list_entry(list, struct drm_mm_node, fl_entry);
wasted = 0;
- if (entry->size < size)
+ if (entry->size < size)
continue;
if (alignment) {
register unsigned tmp = entry->start % alignment;
- if (tmp)
+ if (tmp)
wasted += alignment - tmp;
}
void (*reg_destroy)(struct drm_reg *));
/*
- * drm_bo_lock.c
+ * drm_bo_lock.c
* Simple replacement for the hardware lock on buffer manager init and clean.
*/
extern void drm_bo_init_lock(struct drm_bo_lock *lock);
extern void drm_bo_read_unlock(struct drm_bo_lock *lock);
extern int drm_bo_read_lock(struct drm_bo_lock *lock);
-extern int drm_bo_write_lock(struct drm_bo_lock *lock,
+extern int drm_bo_write_lock(struct drm_bo_lock *lock,
struct drm_file *file_priv);
-extern int drm_bo_write_unlock(struct drm_bo_lock *lock,
+extern int drm_bo_write_unlock(struct drm_bo_lock *lock,
struct drm_file *file_priv);
#ifdef CONFIG_DEBUG_MUTEXES
#define DRM_COPY_TO_USER(arg1, arg2, arg3) \
copy_to_user(arg1, arg2, arg3)
/* Macros for copyfrom user, but checking readability only once */
-#define DRM_VERIFYAREA_READ( uaddr, size ) \
+#define DRM_VERIFYAREA_READ( uaddr, size ) \
(access_ok( VERIFY_READ, uaddr, size) ? 0 : -EFAULT)
-#define DRM_COPY_FROM_USER_UNCHECKED(arg1, arg2, arg3) \
+#define DRM_COPY_FROM_USER_UNCHECKED(arg1, arg2, arg3) \
__copy_from_user(arg1, arg2, arg3)
#define DRM_COPY_TO_USER_UNCHECKED(arg1, arg2, arg3) \
__copy_to_user(arg1, arg2, arg3)
#define DRM_SPINLOCK_IRQSAVE(l, _flags) spin_lock_irqsave(l, _flags);
#define DRM_SPINUNLOCK_IRQRESTORE(l, _flags) spin_unlock_irqrestore(l, _flags);
#define DRM_SPINLOCK_ASSERT(l) do {} while (0)
-
DRM_DEBUG("sg alloc handle = %08lx\n", entry->handle);
DRM_DEBUG("sg alloc virtual = %p\n", entry->virtual);
- for (i = (unsigned long)entry->virtual, j = 0; j < pages;
+ for (i = (unsigned long)entry->virtual, j = 0; j < pages;
i += PAGE_SIZE, j++) {
entry->pagelist[j] = vmalloc_to_page((void *)i);
if (!entry->pagelist[j])
mutex_init(&dev->bm.evict_mutex);
idr_init(&dev->drw_idr);
-
+
dev->pdev = pdev;
dev->pci_device = pdev->device;
dev->pci_vendor = pdev->vendor;
/*294*/ volatile unsigned int xpmask; /* X PlaneMask */
/*298*/ volatile unsigned int ypmask; /* Y PlaneMask */
/*29c*/ volatile unsigned int zpmask; /* Z PlaneMask */
-/*2a0*/ ffb_auxclip auxclip[4]; /* Auxilliary Viewport Clip */
+/*2a0*/ ffb_auxclip auxclip[4]; /* Auxilliary Viewport Clip */
/* New 3dRAM III support regs */
/*2c0*/ volatile unsigned int rawblend2;
int prom_node;
enum ffb_chip_type ffb_type;
u64 card_phys_base;
- struct miscdevice miscdev;
+ struct miscdevice miscdev;
/* Controller registers. */
ffb_fbcPtr regs;
#define I810_BUF_FREE 2
#define I810_BUF_CLIENT 1
-#define I810_BUF_HARDWARE 0
+#define I810_BUF_HARDWARE 0
#define I810_BUF_UNMAPPED 0
#define I810_BUF_MAPPED 1
drm_i810_private_t *dev_priv = dev->dev_private;
RING_LOCALS;
-/* printk("%s\n", __FUNCTION__); */
+/* printk("%s\n", __FUNCTION__); */
i810_kernel_lost_context(dev);
int i, ret = 0;
RING_LOCALS;
-/* printk("%s\n", __FUNCTION__); */
+/* printk("%s\n", __FUNCTION__); */
i810_kernel_lost_context(dev);
* DEALINGS IN THE SOFTWARE.
*
* Authors: Rickard E. (Rik) Faith <faith@valinux.com>
- * Jeff Hartmann <jhartmann@valinux.com>
+ * Jeff Hartmann <jhartmann@valinux.com>
*
*/
#define I810_ADDR(reg) (I810_BASE(reg) + reg)
#define I810_DEREF(reg) *(__volatile__ int *)I810_ADDR(reg)
#define I810_READ(reg) I810_DEREF(reg)
-#define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0)
+#define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0)
#define I810_DEREF16(reg) *(__volatile__ u16 *)I810_ADDR(reg)
#define I810_READ16(reg) I810_DEREF16(reg)
#define I810_WRITE16(reg,val) do { I810_DEREF16(reg) = val; } while (0)
} while (0)
#define ADVANCE_LP_RING() do { \
- if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n"); \
+ if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n"); \
dev_priv->ring.tail = outring; \
I810_WRITE(LP_RING + RING_TAIL, outring); \
} while(0)
-#define OUT_RING(n) do { \
+#define OUT_RING(n) do { \
if (I810_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
*(volatile unsigned int *)(virt + outring) = n; \
outring += 4; \
outring &= ringmask; \
} while (0)
-#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
+#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
#define CMD_REPORT_HEAD (7<<23)
#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
#define I810REG_HWSTAM 0x02098
#define I810REG_INT_IDENTITY_R 0x020a4
-#define I810REG_INT_MASK_R 0x020a8
+#define I810REG_INT_MASK_R 0x020a8
#define I810REG_INT_ENABLE_R 0x020a0
-#define LP_RING 0x2030
-#define HP_RING 0x2040
-#define RING_TAIL 0x00
+#define LP_RING 0x2030
+#define HP_RING 0x2040
+#define RING_TAIL 0x00
#define TAIL_ADDR 0x000FFFF8
-#define RING_HEAD 0x04
-#define HEAD_WRAP_COUNT 0xFFE00000
-#define HEAD_WRAP_ONE 0x00200000
-#define HEAD_ADDR 0x001FFFFC
-#define RING_START 0x08
-#define START_ADDR 0x00FFFFF8
-#define RING_LEN 0x0C
-#define RING_NR_PAGES 0x000FF000
-#define RING_REPORT_MASK 0x00000006
-#define RING_REPORT_64K 0x00000002
-#define RING_REPORT_128K 0x00000004
-#define RING_NO_REPORT 0x00000000
-#define RING_VALID_MASK 0x00000001
-#define RING_VALID 0x00000001
-#define RING_INVALID 0x00000000
+#define RING_HEAD 0x04
+#define HEAD_WRAP_COUNT 0xFFE00000
+#define HEAD_WRAP_ONE 0x00200000
+#define HEAD_ADDR 0x001FFFFC
+#define RING_START 0x08
+#define START_ADDR 0x00FFFFF8
+#define RING_LEN 0x0C
+#define RING_NR_PAGES 0x000FF000
+#define RING_REPORT_MASK 0x00000006
+#define RING_REPORT_64K 0x00000002
+#define RING_REPORT_128K 0x00000004
+#define RING_NO_REPORT 0x00000000
+#define RING_VALID_MASK 0x00000001
+#define RING_VALID 0x00000001
+#define RING_INVALID 0x00000000
#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
#define SC_UPDATE_SCISSOR (0x1<<1)
/**************************************************************************
- *
+ *
* Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
- *
- *
+ *
+ *
**************************************************************************/
/*
* Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
}
/*
- * Flip destination ttm into cached-coherent AGP,
+ * Flip destination ttm into cached-coherent AGP,
* then blit and subsequently move out again.
*/
#endif
static inline void drm_cache_flush_addr(void *virt)
-{
+{
int i;
for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size)
pci_write_config_dword(pdev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
} else {
u64 l64;
-
+
temp_lo &= ~0x1;
l64 = ((u64)temp_hi << 32) | temp_lo;
/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
*/
/*
- *
+ *
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
+ *
*/
#include "drmP.h"
I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
-
+
/* Restore plane info */
I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
if (IS_I965G(dev))
I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
udelay(150);
-
+
/* Restore mode */
I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
/**************************************************************************
- *
+ *
* Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
- *
- *
+ *
+ *
**************************************************************************/
/*
* Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
if (dev_priv->fence_irq_on && !fc->pending_exe_flush) {
i915_user_irq_off(dev_priv);
dev_priv->fence_irq_on = 0;
- } else if (!dev_priv->fence_irq_on && fc->pending_exe_flush) {
+ } else if (!dev_priv->fence_irq_on && fc->pending_exe_flush) {
i915_user_irq_on(dev_priv);
dev_priv->fence_irq_on = 1;
}
*
* 32-bit ioctl compatibility routines for the i915 DRM.
*
- * \author Alan Hourihane <alanh@fairlite.demon.co.uk>
+ * \author Alan Hourihane <alanh@fairlite.demon.co.uk>
*
*
* Copyright (C) Paul Mackerras 2005
{
drm_i915_batchbuffer32_t batchbuffer32;
drm_i915_batchbuffer_t __user *batchbuffer;
-
+
if (copy_from_user
(&batchbuffer32, (void __user *)arg, sizeof(batchbuffer32)))
return -EFAULT;
-
+
batchbuffer = compat_alloc_user_space(sizeof(*batchbuffer));
if (!access_ok(VERIFY_WRITE, batchbuffer, sizeof(*batchbuffer))
|| __put_user(batchbuffer32.start, &batchbuffer->start)
|| __put_user((int __user *)(unsigned long)batchbuffer32.cliprects,
&batchbuffer->cliprects))
return -EFAULT;
-
+
return drm_ioctl(file->f_dentry->d_inode, file,
DRM_IOCTL_I915_BATCHBUFFER,
(unsigned long) batchbuffer);
{
drm_i915_cmdbuffer32_t cmdbuffer32;
drm_i915_cmdbuffer_t __user *cmdbuffer;
-
+
if (copy_from_user
(&cmdbuffer32, (void __user *)arg, sizeof(cmdbuffer32)))
return -EFAULT;
-
+
cmdbuffer = compat_alloc_user_space(sizeof(*cmdbuffer));
if (!access_ok(VERIFY_WRITE, cmdbuffer, sizeof(*cmdbuffer))
|| __put_user((int __user *)(unsigned long)cmdbuffer32.buf,
|| __put_user((int __user *)(unsigned long)cmdbuffer32.cliprects,
&cmdbuffer->cliprects))
return -EFAULT;
-
+
return drm_ioctl(file->f_dentry->d_inode, file,
DRM_IOCTL_I915_CMDBUFFER, (unsigned long) cmdbuffer);
}
if (nr < DRM_COMMAND_BASE)
return drm_compat_ioctl(filp, cmd, arg);
-
+
if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(i915_compat_ioctls))
fn = i915_compat_ioctls[nr - DRM_COMMAND_BASE];
* device is 0x0021 (HB6 Universal PCI-PCI bridge), we reject the
* device.
*/
-
+
if ((pdev->device == 0x0525) && pdev->bus->self
&& (pdev->bus->self->vendor == 0x3388)
&& (pdev->bus->self->device == 0x0021) ) {
typedef struct drm32_mga_init {
int func;
- u32 sarea_priv_offset;
+ u32 sarea_priv_offset;
int chipset;
- int sgram;
+ int sgram;
unsigned int maccess;
- unsigned int fb_cpp;
+ unsigned int fb_cpp;
unsigned int front_offset, front_pitch;
- unsigned int back_offset, back_pitch;
- unsigned int depth_cpp;
- unsigned int depth_offset, depth_pitch;
- unsigned int texture_offset[MGA_NR_TEX_HEAPS];
- unsigned int texture_size[MGA_NR_TEX_HEAPS];
+ unsigned int back_offset, back_pitch;
+ unsigned int depth_cpp;
+ unsigned int depth_offset, depth_pitch;
+ unsigned int texture_offset[MGA_NR_TEX_HEAPS];
+ unsigned int texture_size[MGA_NR_TEX_HEAPS];
u32 fb_offset;
u32 mmio_offset;
u32 status_offset;
drm_mga_init32_t init32;
drm_mga_init_t __user *init;
int err = 0, i;
-
+
if (copy_from_user(&init32, (void __user *)arg, sizeof(init32)))
return -EFAULT;
-
+
init = compat_alloc_user_space(sizeof(*init));
if (!access_ok(VERIFY_WRITE, init, sizeof(*init))
|| __put_user(init32.func, &init->func)
|| __put_user(init32.primary_offset, &init->primary_offset)
|| __put_user(init32.buffers_offset, &init->buffers_offset))
return -EFAULT;
-
+
for (i=0; i<MGA_NR_TEX_HEAPS; i++)
{
err |= __put_user(init32.texture_offset[i], &init->texture_offset[i]);
}
if (err)
return -EFAULT;
-
+
return drm_ioctl(file->f_dentry->d_inode, file,
DRM_IOCTL_MGA_INIT, (unsigned long) init);
}
{
drm_mga_getparam32_t getparam32;
drm_mga_getparam_t __user *getparam;
-
+
if (copy_from_user(&getparam32, (void __user *)arg, sizeof(getparam32)))
return -EFAULT;
|| __put_user((void __user *)(unsigned long)getparam32.value, &getparam->value))
return -EFAULT;
- return drm_ioctl(file->f_dentry->d_inode, file,
+ return drm_ioctl(file->f_dentry->d_inode, file,
DRM_IOCTL_MGA_GETPARAM, (unsigned long)getparam);
}
return -EFAULT;
if (copy_to_user((void __user *)arg, &dma_bootstrap32,
- sizeof(dma_bootstrap32)))
+ sizeof(dma_bootstrap32)))
return -EFAULT;
return 0;
if (nr < DRM_COMMAND_BASE)
return drm_compat_ioctl(filp, cmd, arg);
-
+
if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls))
fn = mga_compat_ioctls[nr - DRM_COMMAND_BASE];
man->io_size = nouveau_mem_fb_amount(dev);
break;
case DRM_BO_MEM_PRIV0:
- /* Unmappable VRAM */
+ /* Unmappable VRAM */
man->flags = _DRM_FLAG_MEMTYPE_CMA;
man->drm_bus_maptype = 0;
break;
.move = nouveau_bo_move,
.ttm_cache_flush= nouveau_bo_flush_ttm
};
-
.probe = probe,
.remove = __devexit_p(drm_cleanup_pci),
},
-
+
.bo_driver = &nouveau_bo_driver,
.fence_driver = &nouveau_fence_driver,
.emit = nouveau_fence_emit,
.poke_flush = nouveau_fence_poke_flush
};
-
if (nvbe->is_bound) {
struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
unsigned int pte;
-
+
pte = nvbe->pte_start;
while (pte < (nvbe->pte_start + nvbe->pages)) {
uint64_t pteval = dev_priv->gart_info.sg_dummy_bus;
DRM_ERROR("Unimplemented on NV50\n");
return -EINVAL;
}
-
{
drm_r128_init32_t init32;
drm_r128_init_t __user *init;
-
+
if (copy_from_user(&init32, (void __user *)arg, sizeof(init32)))
return -EFAULT;
-
+
init = compat_alloc_user_space(sizeof(*init));
if (!access_ok(VERIFY_WRITE, init, sizeof(*init))
|| __put_user(init32.func, &init->func)
|| __put_user(init32.agp_textures_offset,
&init->agp_textures_offset))
return -EFAULT;
-
+
return drm_ioctl(file->f_dentry->d_inode, file,
DRM_IOCTL_R128_INIT, (unsigned long)init);
}
return snprintf(buf, PAGE_SIZE, "%s\n",
(family < CHIP_R200) ? "radeon" :
((family < CHIP_R300) ? "r200" :
- "r300"));
+ "r300"));
}
static struct pci_device_id pciidlist[] = {
return 0;
}
}
-
+
/*
* Implement a device switch here if needed
*/
man->drm_bus_maptype = 0;
break;
- case DRM_BO_MEM_TT:
+ case DRM_BO_MEM_TT:
/* Dynamic agpgart memory */
-
+
if (!(drm_core_has_AGP(dev) && dev->agp)) {
DRM_ERROR("AGP is not enabled for memory type %u\n",
(unsigned)type);
/* Only to get pte protection right. */
- man->drm_bus_maptype = _DRM_AGP;
+ man->drm_bus_maptype = _DRM_AGP;
break;
- case DRM_BO_MEM_VRAM:
+ case DRM_BO_MEM_VRAM:
/* "On-card" video ram */
-
+
man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE | _DRM_FLAG_NEEDS_IOREMAP;
man->drm_bus_maptype = _DRM_FRAME_BUFFER;
man->io_addr = NULL;
return via_vram_info(dev, &man->io_offset, &man->io_size);
break;
- case DRM_BO_MEM_PRIV0:
+ case DRM_BO_MEM_PRIV0:
/* Pre-bound agpgart memory */
-
+
if (!(drm_core_has_AGP(dev) && dev->agp)) {
DRM_ERROR("AGP is not enabled for memory type %u\n",
(unsigned)type);
/* via_dmablit.c -- PCI DMA BitBlt support for the VIA Unichrome/Pro
- *
+ *
* Copyright (C) 2005 Thomas Hellstrom, All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Authors:
+ * Authors:
* Thomas Hellstrom.
* Partially based on code obtained from Digeo Inc.
*/
/*
- * Unmaps the DMA mappings.
- * FIXME: Is this a NoOp on x86? Also
- * FIXME: What happens if this one is called and a pending blit has previously done
- * the same DMA mappings?
+ * Unmaps the DMA mappings.
+ * FIXME: Is this a NoOp on x86? Also
+ * FIXME: What happens if this one is called and a pending blit has previously done
+ * the same DMA mappings?
*/
#include "drmP.h"
int num_desc = vsg->num_desc;
unsigned cur_descriptor_page = num_desc / vsg->descriptors_per_page;
unsigned descriptor_this_page = num_desc % vsg->descriptors_per_page;
- drm_via_descriptor_t *desc_ptr = vsg->desc_pages[cur_descriptor_page] +
+ drm_via_descriptor_t *desc_ptr = vsg->desc_pages[cur_descriptor_page] +
descriptor_this_page;
dma_addr_t next = vsg->chain_start;
if (descriptor_this_page-- == 0) {
cur_descriptor_page--;
descriptor_this_page = vsg->descriptors_per_page - 1;
- desc_ptr = vsg->desc_pages[cur_descriptor_page] +
+ desc_ptr = vsg->desc_pages[cur_descriptor_page] +
descriptor_this_page;
}
dma_unmap_single(&pdev->dev, next, sizeof(*desc_ptr), DMA_TO_DEVICE);
static void
via_map_blit_for_device(struct pci_dev *pdev,
const drm_via_dmablit_t *xfer,
- drm_via_sg_info_t *vsg,
+ drm_via_sg_info_t *vsg,
int mode)
{
unsigned cur_descriptor_page = 0;
dma_addr_t next = 0 | VIA_DMA_DPR_EC;
drm_via_descriptor_t *desc_ptr = NULL;
- if (mode == 1)
+ if (mode == 1)
desc_ptr = vsg->desc_pages[cur_descriptor_page];
for (cur_line = 0; cur_line < xfer->num_lines; ++cur_line) {
line_len = xfer->line_length;
cur_fb = fb_addr;
cur_mem = mem_addr;
-
+
while (line_len > 0) {
remaining_len = min(PAGE_SIZE-VIA_PGOFF(cur_mem), line_len);
VIA_PGOFF(cur_mem), remaining_len,
vsg->direction);
desc_ptr->dev_addr = cur_fb;
-
+
desc_ptr->size = remaining_len;
desc_ptr->next = (uint32_t) next;
- next = dma_map_single(&pdev->dev, desc_ptr, sizeof(*desc_ptr),
+ next = dma_map_single(&pdev->dev, desc_ptr, sizeof(*desc_ptr),
DMA_TO_DEVICE);
desc_ptr++;
if (++num_descriptors_this_page >= vsg->descriptors_per_page) {
desc_ptr = vsg->desc_pages[++cur_descriptor_page];
}
}
-
+
num_desc++;
cur_mem += remaining_len;
cur_fb += remaining_len;
}
-
+
mem_addr += xfer->mem_stride;
fb_addr += xfer->fb_stride;
}
}
/*
- * Function that frees up all resources for a blit. It is usable even if the
+ * Function that frees up all resources for a blit. It is usable even if the
* blit info has only been partially built as long as the status enum is consistent
* with the actual status of the used resources.
*/
static void
-via_free_sg_info(struct pci_dev *pdev, drm_via_sg_info_t *vsg)
+via_free_sg_info(struct pci_dev *pdev, drm_via_sg_info_t *vsg)
{
struct page *page;
int i;
case dr_via_pages_locked:
for (i=0; i<vsg->num_pages; ++i) {
if ( NULL != (page = vsg->pages[i])) {
- if (! PageReserved(page) && (DMA_FROM_DEVICE == vsg->direction))
+ if (! PageReserved(page) && (DMA_FROM_DEVICE == vsg->direction))
SetPageDirty(page);
page_cache_release(page);
}
vsg->bounce_buffer = NULL;
}
vsg->free_on_sequence = 0;
-}
+}
/*
* Fire a blit engine.
VIA_WRITE(VIA_PCI_DMA_MAR0 + engine*0x10, 0);
VIA_WRITE(VIA_PCI_DMA_DAR0 + engine*0x10, 0);
- VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD |
+ VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD |
VIA_DMA_CSR_DE);
VIA_WRITE(VIA_PCI_DMA_MR0 + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE);
VIA_WRITE(VIA_PCI_DMA_BCR0 + engine*0x10, 0);
{
int ret;
unsigned long first_pfn = VIA_PFN(xfer->mem_addr);
- vsg->num_pages = VIA_PFN(xfer->mem_addr + (xfer->num_lines * xfer->mem_stride -1)) -
+ vsg->num_pages = VIA_PFN(xfer->mem_addr + (xfer->num_lines * xfer->mem_stride -1)) -
first_pfn + 1;
-
+
if (NULL == (vsg->pages = vmalloc(sizeof(struct page *) * vsg->num_pages)))
return -ENOMEM;
memset(vsg->pages, 0, sizeof(struct page *) * vsg->num_pages);
down_read(¤t->mm->mmap_sem);
ret = get_user_pages(current, current->mm, (unsigned long) xfer->mem_addr,
- vsg->num_pages, (vsg->direction == DMA_FROM_DEVICE),
+ vsg->num_pages, (vsg->direction == DMA_FROM_DEVICE),
0, vsg->pages, NULL);
up_read(¤t->mm->mmap_sem);
if (ret != vsg->num_pages) {
- if (ret < 0)
+ if (ret < 0)
return ret;
vsg->state = dr_via_pages_locked;
return -EINVAL;
* quite large for some blits, and pages don't need to be contingous.
*/
-static int
+static int
via_alloc_desc_pages(drm_via_sg_info_t *vsg)
{
int i;
-
+
vsg->descriptors_per_page = PAGE_SIZE / sizeof( drm_via_descriptor_t);
- vsg->num_desc_pages = (vsg->num_desc + vsg->descriptors_per_page - 1) /
+ vsg->num_desc_pages = (vsg->num_desc + vsg->descriptors_per_page - 1) /
vsg->descriptors_per_page;
- if (NULL == (vsg->desc_pages = kmalloc(sizeof(void *) * vsg->num_desc_pages, GFP_KERNEL)))
+ if (NULL == (vsg->desc_pages = kmalloc(sizeof(void *) * vsg->num_desc_pages, GFP_KERNEL)))
return -ENOMEM;
-
+
memset(vsg->desc_pages, 0, sizeof(void *) * vsg->num_desc_pages);
vsg->state = dr_via_desc_pages_alloc;
for (i=0; i<vsg->num_desc_pages; ++i) {
- if (NULL == (vsg->desc_pages[i] =
+ if (NULL == (vsg->desc_pages[i] =
(drm_via_descriptor_t *) __get_free_page(GFP_KERNEL)))
return -ENOMEM;
}
vsg->num_desc);
return 0;
}
-
+
static void
via_abort_dmablit(struct drm_device *dev, int engine)
{
{
drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
- VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD);
+ VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD);
}
* task. Basically the task of the interrupt handler is to submit a new blit to the engine, while
* the workqueue task takes care of processing associated with the old blit.
*/
-
+
void
via_dmablit_handler(struct drm_device *dev, int engine, int from_irq)
{
spin_lock_irqsave(&blitq->blit_lock, irqsave);
}
- done_transfer = blitq->is_active &&
+ done_transfer = blitq->is_active &&
(( status = VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD);
- done_transfer = done_transfer || ( blitq->aborting && !(status & VIA_DMA_CSR_DE));
+ done_transfer = done_transfer || ( blitq->aborting && !(status & VIA_DMA_CSR_DE));
cur = blitq->cur;
if (done_transfer) {
blitq->blits[cur]->aborted = blitq->aborting;
blitq->done_blit_handle++;
- DRM_WAKEUP(blitq->blit_queue + cur);
+ DRM_WAKEUP(blitq->blit_queue + cur);
cur++;
- if (cur >= VIA_NUM_BLIT_SLOTS)
+ if (cur >= VIA_NUM_BLIT_SLOTS)
cur = 0;
blitq->cur = cur;
blitq->is_active = 0;
blitq->aborting = 0;
- schedule_work(&blitq->wq);
+ schedule_work(&blitq->wq);
} else if (blitq->is_active && time_after_eq(jiffies, blitq->end)) {
blitq->aborting = 1;
blitq->end = jiffies + DRM_HZ;
}
-
+
if (!blitq->is_active) {
if (blitq->num_outstanding) {
via_fire_dmablit(dev, blitq->blits[cur], engine);
}
via_dmablit_engine_off(dev, engine);
}
- }
+ }
if (from_irq) {
spin_unlock(&blitq->blit_lock);
} else {
spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
}
-}
+}
return active;
}
-
+
/*
* Sync. Wait for at least three seconds for the blit to be performed.
*/
static int
-via_dmablit_sync(struct drm_device *dev, uint32_t handle, int engine)
+via_dmablit_sync(struct drm_device *dev, uint32_t handle, int engine)
{
drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
int ret = 0;
if (via_dmablit_active(blitq, engine, handle, &queue)) {
- DRM_WAIT_ON(ret, *queue, 3 * DRM_HZ,
+ DRM_WAIT_ON(ret, *queue, 3 * DRM_HZ,
!via_dmablit_active(blitq, engine, handle, NULL));
}
DRM_DEBUG("DMA blit sync handle 0x%x engine %d returned %d\n",
handle, engine, ret);
-
+
return ret;
}
struct drm_device *dev = blitq->dev;
int engine = (int)
(blitq - ((drm_via_private_t *)dev->dev_private)->blit_queues);
-
- DRM_DEBUG("Polling timer called for engine %d, jiffies %lu\n", engine,
+
+ DRM_DEBUG("Polling timer called for engine %d, jiffies %lu\n", engine,
(unsigned long) jiffies);
via_dmablit_handler(dev, engine, 0);
-
+
if (!timer_pending(&blitq->poll_timer)) {
blitq->poll_timer.expires = jiffies+1;
add_timer(&blitq->poll_timer);
*/
-static void
+static void
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
via_dmablit_workqueue(void *data)
#else
unsigned long irqsave;
drm_via_sg_info_t *cur_sg;
int cur_released;
-
-
- DRM_DEBUG("Workqueue task called for blit engine %ld\n",(unsigned long)
+
+
+ DRM_DEBUG("Workqueue task called for blit engine %ld\n",(unsigned long)
(blitq - ((drm_via_private_t *)dev->dev_private)->blit_queues));
spin_lock_irqsave(&blitq->blit_lock, irqsave);
-
+
while(blitq->serviced != blitq->cur) {
cur_released = blitq->serviced++;
DRM_DEBUG("Releasing blit slot %d\n", cur_released);
- if (blitq->serviced >= VIA_NUM_BLIT_SLOTS)
+ if (blitq->serviced >= VIA_NUM_BLIT_SLOTS)
blitq->serviced = 0;
-
+
cur_sg = blitq->blits[cur_released];
blitq->num_free++;
-
+
spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
-
+
DRM_WAKEUP(&blitq->busy_queue);
-
+
via_free_sg_info(dev->pdev, cur_sg);
kfree(cur_sg);
-
+
spin_lock_irqsave(&blitq->blit_lock, irqsave);
}
spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
}
-
+
/*
* Init all blit engines. Currently we use two, but some hardware have 4.
drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
drm_via_blitq_t *blitq;
- pci_set_master(dev->pdev);
-
+ pci_set_master(dev->pdev);
+
for (i=0; i< VIA_NUM_BLIT_ENGINES; ++i) {
blitq = dev_priv->blit_queues + i;
blitq->dev = dev;
init_timer(&blitq->poll_timer);
blitq->poll_timer.function = &via_dmablit_timer;
blitq->poll_timer.data = (unsigned long) blitq;
- }
+ }
}
/*
* Build all info and do all mappings required for a blit.
*/
-
+
static int
via_build_sg_info(struct drm_device *dev, drm_via_sg_info_t *vsg, drm_via_dmablit_t *xfer)
{
int draw = xfer->to_fb;
int ret = 0;
-
+
vsg->direction = (draw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
vsg->bounce_buffer = NULL;
/*
* Below check is a driver limitation, not a hardware one. We
* don't want to lock unused pages, and don't want to incoporate the
- * extra logic of avoiding them. Make sure there are no.
+ * extra logic of avoiding them. Make sure there are no.
* (Not a big limitation anyway.)
*/
if (xfer->num_lines > 2048 || (xfer->num_lines*xfer->mem_stride > (2048*2048*4))) {
DRM_ERROR("Too large PCI DMA bitblt.\n");
return -EINVAL;
- }
+ }
- /*
+ /*
* we allow a negative fb stride to allow flipping of images in
- * transfer.
+ * transfer.
*/
if (xfer->mem_stride < xfer->line_length ||
((xfer->num_lines > 1) && ((xfer->mem_stride & 15) || (xfer->fb_stride & 3)))) {
DRM_ERROR("Invalid DRM bitblt alignment.\n");
return -EINVAL;
- }
+ }
#endif
if (0 != (ret = via_lock_all_dma_pages(vsg, xfer))) {
return ret;
}
via_map_blit_for_device(dev->pdev, xfer, vsg, 1);
-
+
return 0;
}
-
+
/*
* Reserve one free slot in the blit queue. Will wait for one second for one
* to become available. Otherwise -EBUSY is returned.
*/
-static int
+static int
via_dmablit_grab_slot(drm_via_blitq_t *blitq, int engine)
{
int ret=0;
if (ret) {
return (-EINTR == ret) ? -EAGAIN : ret;
}
-
+
spin_lock_irqsave(&blitq->blit_lock, irqsave);
}
-
+
blitq->num_free--;
spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
* Hand back a free slot if we changed our mind.
*/
-static void
+static void
via_dmablit_release_slot(drm_via_blitq_t *blitq)
{
unsigned long irqsave;
*/
-static int
-via_dmablit(struct drm_device *dev, drm_via_dmablit_t *xfer)
+static int
+via_dmablit(struct drm_device *dev, drm_via_dmablit_t *xfer)
{
drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
drm_via_sg_info_t *vsg;
spin_lock_irqsave(&blitq->blit_lock, irqsave);
blitq->blits[blitq->head++] = vsg;
- if (blitq->head >= VIA_NUM_BLIT_SLOTS)
+ if (blitq->head >= VIA_NUM_BLIT_SLOTS)
blitq->head = 0;
blitq->num_outstanding++;
- xfer->sync.sync_handle = ++blitq->cur_blit_handle;
+ xfer->sync.sync_handle = ++blitq->cur_blit_handle;
spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
xfer->sync.engine = engine;
- via_dmablit_handler(dev, engine, 0);
+ via_dmablit_handler(dev, engine, 0);
return 0;
}
/*
* Sync on a previously submitted blit. Note that the X server use signals extensively, and
* that there is a very big probability that this IOCTL will be interrupted by a signal. In that
- * case it returns with -EAGAIN for the signal to be delivered.
+ * case it returns with -EAGAIN for the signal to be delivered.
* The caller should then reissue the IOCTL. This is similar to what is being done for drmGetLock().
*/
drm_via_blitsync_t *sync = data;
int err;
- if (sync->engine >= VIA_NUM_BLIT_ENGINES)
+ if (sync->engine >= VIA_NUM_BLIT_ENGINES)
return -EINVAL;
err = via_dmablit_sync(dev, sync->sync_handle, sync->engine);
return err;
}
-
+
/*
* Queue a blit and hand back a handle to be used for sync. This IOCTL may be interrupted by a signal
- * while waiting for a free slot in the blit queue. In that case it returns with -EAGAIN and should
+ * while waiting for a free slot in the blit queue. In that case it returns with -EAGAIN and should
* be reissued. See the above IOCTL code.
*/
-int
+int
via_dma_blit( struct drm_device *dev, void *data, struct drm_file *file_priv )
{
drm_via_dmablit_t *xfer = data;
/* via_dmablit.h -- PCI DMA BitBlt support for the VIA Unichrome/Pro
- *
+ *
* Copyright 2005 Thomas Hellstrom.
* All Rights Reserved.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Authors:
+ * Authors:
* Thomas Hellstrom.
* Register info from Digeo Inc.
*/
unsigned cur;
unsigned num_free;
unsigned num_outstanding;
- unsigned long end;
+ unsigned long end;
int aborting;
int is_active;
drm_via_sg_info_t *blits[VIA_NUM_BLIT_SLOTS];
struct work_struct wq;
struct timer_list poll_timer;
} drm_via_blitq_t;
-
-/*
+
+/*
* PCI DMA Registers
* Channels 2 & 3 don't seem to be implemented in hardware.
*/
-
-#define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */
-#define VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */
-#define VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */
-#define VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */
-
-#define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */
-#define VIA_PCI_DMA_DAR1 0xE54 /* Device Address Register of Channel 1 */
-#define VIA_PCI_DMA_BCR1 0xE58 /* Byte Count Register of Channel 1 */
-#define VIA_PCI_DMA_DPR1 0xE5C /* Descriptor Pointer Register of Channel 1 */
-
-#define VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */
-#define VIA_PCI_DMA_DAR2 0xE64 /* Device Address Register of Channel 2 */
-#define VIA_PCI_DMA_BCR2 0xE68 /* Byte Count Register of Channel 2 */
-#define VIA_PCI_DMA_DPR2 0xE6C /* Descriptor Pointer Register of Channel 2 */
-
-#define VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */
-#define VIA_PCI_DMA_DAR3 0xE74 /* Device Address Register of Channel 3 */
-#define VIA_PCI_DMA_BCR3 0xE78 /* Byte Count Register of Channel 3 */
-#define VIA_PCI_DMA_DPR3 0xE7C /* Descriptor Pointer Register of Channel 3 */
-
-#define VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */
-#define VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */
-#define VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */
-#define VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */
-
-#define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */
-#define VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */
-#define VIA_PCI_DMA_CSR2 0xE98 /* Command/Status Register of Channel 2 */
-#define VIA_PCI_DMA_CSR3 0xE9C /* Command/Status Register of Channel 3 */
-
-#define VIA_PCI_DMA_PTR 0xEA0 /* Priority Type Register */
-
-/* Define for DMA engine */
+
+#define VIA_PCI_DMA_MAR0 0xE40 /* Memory Address Register of Channel 0 */
+#define VIA_PCI_DMA_DAR0 0xE44 /* Device Address Register of Channel 0 */
+#define VIA_PCI_DMA_BCR0 0xE48 /* Byte Count Register of Channel 0 */
+#define VIA_PCI_DMA_DPR0 0xE4C /* Descriptor Pointer Register of Channel 0 */
+
+#define VIA_PCI_DMA_MAR1 0xE50 /* Memory Address Register of Channel 1 */
+#define VIA_PCI_DMA_DAR1 0xE54 /* Device Address Register of Channel 1 */
+#define VIA_PCI_DMA_BCR1 0xE58 /* Byte Count Register of Channel 1 */
+#define VIA_PCI_DMA_DPR1 0xE5C /* Descriptor Pointer Register of Channel 1 */
+
+#define VIA_PCI_DMA_MAR2 0xE60 /* Memory Address Register of Channel 2 */
+#define VIA_PCI_DMA_DAR2 0xE64 /* Device Address Register of Channel 2 */
+#define VIA_PCI_DMA_BCR2 0xE68 /* Byte Count Register of Channel 2 */
+#define VIA_PCI_DMA_DPR2 0xE6C /* Descriptor Pointer Register of Channel 2 */
+
+#define VIA_PCI_DMA_MAR3 0xE70 /* Memory Address Register of Channel 3 */
+#define VIA_PCI_DMA_DAR3 0xE74 /* Device Address Register of Channel 3 */
+#define VIA_PCI_DMA_BCR3 0xE78 /* Byte Count Register of Channel 3 */
+#define VIA_PCI_DMA_DPR3 0xE7C /* Descriptor Pointer Register of Channel 3 */
+
+#define VIA_PCI_DMA_MR0 0xE80 /* Mode Register of Channel 0 */
+#define VIA_PCI_DMA_MR1 0xE84 /* Mode Register of Channel 1 */
+#define VIA_PCI_DMA_MR2 0xE88 /* Mode Register of Channel 2 */
+#define VIA_PCI_DMA_MR3 0xE8C /* Mode Register of Channel 3 */
+
+#define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */
+#define VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */
+#define VIA_PCI_DMA_CSR2 0xE98 /* Command/Status Register of Channel 2 */
+#define VIA_PCI_DMA_CSR3 0xE9C /* Command/Status Register of Channel 3 */
+
+#define VIA_PCI_DMA_PTR 0xEA0 /* Priority Type Register */
+
+/* Define for DMA engine */
/* DPR */
#define VIA_DMA_DPR_EC (1<<1) /* end of chain */
#define VIA_DMA_DPR_DDIE (1<<2) /* descriptor done interrupt enable */
dev_priv->vram_initialized = 0;
dev_priv->agp_initialized = 0;
mutex_unlock(&dev->struct_mutex);
-}
+}
int via_mem_alloc(struct drm_device *dev, void *data,
struct drm_file *file_priv)
* @type: Type of the current batch
*
* See section 3.2.2 "Begin" (page 15) of the 3D SPG.
- *
+ *
* This function assumes that @type is on the range [0,3].
*/
unsigned int get_batch_command(enum xgi_batch_type type)
static const unsigned int ports[4] = {
0x30 >> 2, 0x40 >> 2, 0x50 >> 2, 0x20 >> 2
};
-
+
return ports[type];
}
2 - fb
3 - logout
*/
-int xgi_state_change(struct xgi_info * info, unsigned int to,
+int xgi_state_change(struct xgi_info * info, unsigned int to,
unsigned int from)
{
#define STATE_CONSOLE 0
}
xgi_waitfor_pci_idle(info);
-
+
(void) memset(&info->cmdring, 0, sizeof(info->cmdring));
}
}
void xgi_emit_flush(struct xgi_info * info, bool stop)
{
const u32 flush_command[8] = {
- ((0x10 << 24)
+ ((0x10 << 24)
| (BEGIN_BEGIN_IDENTIFICATION_MASK & info->next_sequence)),
BEGIN_LINK_ENABLE_MASK | (0x00004),
0x00000000, 0x00000000,
info->cmdring.ring_offset = 0;
}
- hw_addr = info->cmdring.ring_hw_base
+ hw_addr = info->cmdring.ring_hw_base
+ info->cmdring.ring_offset;
- batch_addr = info->cmdring.ptr
+ batch_addr = info->cmdring.ptr
+ (info->cmdring.ring_offset / 4);
for (i = 0; i < (flush_size / 4); i++) {
struct drm_device *dev = (struct drm_device *) arg;
struct xgi_info *info = dev->dev_private;
const u32 irq_bits = le32_to_cpu(DRM_READ32(info->mmio_map,
- (0x2800
+ (0x2800
+ M2REG_AUTO_LINK_STATUS_ADDRESS)))
& (M2REG_ACTIVE_TIMER_INTERRUPT_MASK
| M2REG_ACTIVE_INTERRUPT_0_MASK
if (irq_bits != 0) {
- DRM_WRITE32(info->mmio_map,
+ DRM_WRITE32(info->mmio_map,
0x2800 + M2REG_AUTO_LINK_SETTING_ADDRESS,
cpu_to_le32(M2REG_AUTO_LINK_SETTING_COMMAND | irq_bits));
xgi_fence_handler(dev);
return 0;
-
+
fail:
drm_free(info, sizeof(*info), DRM_MEM_DRIVER);
return err;
struct drm_file * filp)
{
struct drm_memblock_item *block;
- const char *const mem_name = (alloc->location == XGI_MEMLOC_LOCAL)
+ const char *const mem_name = (alloc->location == XGI_MEMLOC_LOCAL)
? "on-card" : "GART";
return -EINVAL;
}
- if ((alloc->location == XGI_MEMLOC_LOCAL)
+ if ((alloc->location == XGI_MEMLOC_LOCAL)
? !info->fb_heap_initialized : !info->pcie_heap_initialized) {
DRM_ERROR("Attempt to allocate from uninitialized memory "
"pool (0x%08x).\n", alloc->location);
int xgi_fb_heap_init(struct xgi_info * info)
{
int err;
-
+
mutex_lock(&info->dev->struct_mutex);
err = drm_sman_set_range(&info->sman, XGI_MEMLOC_LOCAL,
XGI_FB_HEAP_START,
int xgi_fence_emit_sequence(struct drm_device * dev, uint32_t class,
- uint32_t flags, uint32_t * sequence,
+ uint32_t flags, uint32_t * sequence,
uint32_t * native_type)
{
struct xgi_info * info = dev->dev_private;
u32 handle; /**< User-space: "Handle" to pass to mmap() */
int mtrr; /**< MTRR slot used */
};
-
+
struct drm32_xgi_bootstrap {
struct drm_map32 gart;
};
DRM_WRITE8(map, 0xb057, 8);
while (0 != le32_to_cpu(DRM_READ32(map, 0x2800) & 0xf0000000)) {
- while (0 != ((--time_out) & 0xfff))
+ while (0 != ((--time_out) & 0xfff))
/* empty */ ;
if (0 == time_out) {
DRM_WRITE8(map, 0x3d4, 0x36);
old_36 = DRM_READ8(map, 0x3d5);
DRM_WRITE8(map, 0x3d5, old_36 | 0x10);
-
- while (0 != ((--time_out) & 0xfff))
+
+ while (0 != ((--time_out) & 0xfff))
/* empty */ ;
DRM_WRITE8(map, 0x3d5, old_36);
DRM_WRITE8(map, 0xb057, 0);
}
-
+
bool xgi_ge_irq_handler(struct xgi_info * info)
{
const u32 int_status = le32_to_cpu(DRM_READ32(info->mmio_map, 0x2810));
/* Check GE on/off */
if (0 == (0xffffc0f0 & int_status)) {
if (0 != (0x1000 & int_status)) {
- /* We got GE stall interrupt.
+ /* We got GE stall interrupt.
*/
DRM_WRITE32(info->mmio_map, 0x2810,
cpu_to_le32(int_status | 0x04000000));
printk("%1x ", i);
for (j = 0; j < 0x10; j++) {
- u8 temp = DRM_READ8(info->mmio_map,
+ u8 temp = DRM_READ8(info->mmio_map,
regbase + (i * 0x10) + j);
printk("%3x", temp);
}
/****************************************************************************
- * Copyright (C) 2003-2006 by XGI Technology, Taiwan.
+ * Copyright (C) 2003-2006 by XGI Technology, Taiwan.
*
* All Rights Reserved.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
+ * a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
/* Mask: Make sure the buffer is in cached memory when mapped
* Flags: Acknowledge.
* Buffers allocated with this flag should not be used for suballocators
- * This type may have issues on CPUs with over-aggressive caching
+ * This type may have issues on CPUs with over-aggressive caching
* http://marc.info/?l=linux-kernel&m=102376926732464&w=2
*/
#define DRM_BO_FLAG_CACHED_MAPPED (1ULL << 19)
#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
-#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
+#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
#endif
/** Maximum number of drawables in the SAREA */
-#define SAREA_MAX_DRAWABLES 256
+#define SAREA_MAX_DRAWABLES 256
#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000
/*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
+ *
*/
#include "drmP.h"
/* Enable vblank on pipe A for older X servers
*/
- dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
+ dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
/* Program Hardware Status Page */
if (!IS_G33(dev)) {
- dev_priv->status_page_dmah =
+ dev_priv->status_page_dmah =
drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
if (!dev_priv->status_page_dmah) {
{
int ret = do_validate_cmd(cmd);
-/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
+/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
return ret;
}
OUT_RING(cmd);
}
}
-
+
if (dwords & 1)
OUT_RING(0);
ADVANCE_LP_RING();
-
+
return 0;
}
int ret = 0;
memset(&relocatee, 0, sizeof(relocatee));
-
+
mutex_lock(&dev->struct_mutex);
relocatee.buf = drm_lookup_buffer_object(file_priv, buf_handle, 1);
mutex_unlock(&dev->struct_mutex);
ret = -EINVAL;
goto out_err;
}
-
+
while (buf_reloc_handle) {
ret = i915_process_relocs(file_priv, buf_handle, &buf_reloc_handle, &relocatee, buffers, buf_count);
if (ret) {
break;
}
}
-
+
mutex_lock(&dev->struct_mutex);
drm_bo_usage_deref_locked(&relocatee.buf);
mutex_unlock(&dev->struct_mutex);
-
+
out_err:
return ret;
}
ret = drm_bo_read_lock(&dev->bm.bm_lock);
- if (ret)
+ if (ret)
return ret;
/*
* The cmdbuf_mutex makes sure the validate-submit-fence
- * operation is atomic.
+ * operation is atomic.
*/
ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);
I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
0x2350,
8
- }
+ }
};
static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
{
uint32_t buf[8];
drm_i915_private_t *dev_priv = dev->dev_private;
- drm_i915_mmio_entry_t *e;
+ drm_i915_mmio_entry_t *e;
drm_i915_mmio_t *mmio = data;
void __iomem *base;
int i;
/*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
+ *
*/
#ifndef _I915_DRM_H_
unsigned int sequence;
} drm_i915_vblank_swap_t;
-#define I915_MMIO_READ 0
+#define I915_MMIO_READ 0
#define I915_MMIO_WRITE 1
-#define I915_MMIO_MAY_READ 0x1
-#define I915_MMIO_MAY_WRITE 0x2
+#define I915_MMIO_MAY_READ 0x1
+#define I915_MMIO_MAY_WRITE 0x2
#define MMIO_REGS_IA_PRIMATIVES_COUNT 0
#define MMIO_REGS_IA_VERTICES_COUNT 1
typedef struct drm_i915_mmio {
unsigned int read_write:1;
unsigned int reg:31;
- void __user *data;
+ void __user *data;
} drm_i915_mmio_t;
typedef struct drm_i915_hws_addr {
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
*/
/*
- *
+ *
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
+ *
*/
#ifndef _I915_DRV_H_
drm_i915_vbl_swap_t vbl_swaps;
unsigned int swaps_pending;
- /* Register state */
+ /* Register state */
u8 saveLBB;
- u32 saveDSPACNTR;
- u32 saveDSPBCNTR;
- u32 savePIPEACONF;
- u32 savePIPEBCONF;
- u32 savePIPEASRC;
- u32 savePIPEBSRC;
- u32 saveFPA0;
- u32 saveFPA1;
- u32 saveDPLL_A;
- u32 saveDPLL_A_MD;
- u32 saveHTOTAL_A;
- u32 saveHBLANK_A;
- u32 saveHSYNC_A;
- u32 saveVTOTAL_A;
- u32 saveVBLANK_A;
- u32 saveVSYNC_A;
+ u32 saveDSPACNTR;
+ u32 saveDSPBCNTR;
+ u32 savePIPEACONF;
+ u32 savePIPEBCONF;
+ u32 savePIPEASRC;
+ u32 savePIPEBSRC;
+ u32 saveFPA0;
+ u32 saveFPA1;
+ u32 saveDPLL_A;
+ u32 saveDPLL_A_MD;
+ u32 saveHTOTAL_A;
+ u32 saveHBLANK_A;
+ u32 saveHSYNC_A;
+ u32 saveVTOTAL_A;
+ u32 saveVBLANK_A;
+ u32 saveVSYNC_A;
u32 saveBCLRPAT_A;
- u32 saveDSPASTRIDE;
- u32 saveDSPASIZE;
- u32 saveDSPAPOS;
- u32 saveDSPABASE;
- u32 saveDSPASURF;
+ u32 saveDSPASTRIDE;
+ u32 saveDSPASIZE;
+ u32 saveDSPAPOS;
+ u32 saveDSPABASE;
+ u32 saveDSPASURF;
u32 saveDSPATILEOFF;
u32 savePFIT_PGM_RATIOS;
u32 saveBLC_PWM_CTL;
u32 saveBLC_PWM_CTL2;
- u32 saveFPB0;
- u32 saveFPB1;
- u32 saveDPLL_B;
- u32 saveDPLL_B_MD;
- u32 saveHTOTAL_B;
- u32 saveHBLANK_B;
- u32 saveHSYNC_B;
- u32 saveVTOTAL_B;
- u32 saveVBLANK_B;
- u32 saveVSYNC_B;
+ u32 saveFPB0;
+ u32 saveFPB1;
+ u32 saveDPLL_B;
+ u32 saveDPLL_B_MD;
+ u32 saveHTOTAL_B;
+ u32 saveHBLANK_B;
+ u32 saveHSYNC_B;
+ u32 saveVTOTAL_B;
+ u32 saveVBLANK_B;
+ u32 saveVSYNC_B;
u32 saveBCLRPAT_B;
- u32 saveDSPBSTRIDE;
- u32 saveDSPBSIZE;
- u32 saveDSPBPOS;
- u32 saveDSPBBASE;
- u32 saveDSPBSURF;
+ u32 saveDSPBSTRIDE;
+ u32 saveDSPBSIZE;
+ u32 saveDSPBPOS;
+ u32 saveDSPBBASE;
+ u32 saveDSPBSURF;
u32 saveDSPBTILEOFF;
- u32 saveVCLK_DIVISOR_VGA0;
- u32 saveVCLK_DIVISOR_VGA1;
- u32 saveVCLK_POST_DIV;
- u32 saveVGACNTRL;
- u32 saveADPA;
- u32 saveLVDS;
+ u32 saveVCLK_DIVISOR_VGA0;
+ u32 saveVCLK_DIVISOR_VGA1;
+ u32 saveVCLK_POST_DIV;
+ u32 saveVGACNTRL;
+ u32 saveADPA;
+ u32 saveLVDS;
u32 saveLVDSPP_ON;
u32 saveLVDSPP_OFF;
- u32 saveDVOA;
- u32 saveDVOB;
- u32 saveDVOC;
- u32 savePP_ON;
- u32 savePP_OFF;
- u32 savePP_CONTROL;
- u32 savePP_CYCLE;
- u32 savePFIT_CONTROL;
- u32 save_palette_a[256];
- u32 save_palette_b[256];
+ u32 saveDVOA;
+ u32 saveDVOB;
+ u32 saveDVOC;
+ u32 savePP_ON;
+ u32 savePP_OFF;
+ u32 savePP_CONTROL;
+ u32 savePP_CYCLE;
+ u32 savePFIT_CONTROL;
+ u32 save_palette_a[256];
+ u32 save_palette_b[256];
u32 saveFBC_CFB_BASE;
u32 saveFBC_LL_BASE;
u32 saveFBC_CONTROL;
u32 saveFBC_CONTROL2;
- u32 saveSWF0[16];
- u32 saveSWF1[16];
- u32 saveSWF2[3];
+ u32 saveSWF0[16];
+ u32 saveSWF1[16];
+ u32 saveSWF2[3];
u8 saveMSR;
u8 saveSR[8];
u8 saveGR[24];
extern void i915_fence_handler(struct drm_device *dev);
extern int i915_fence_emit_sequence(struct drm_device *dev, uint32_t class,
uint32_t flags,
- uint32_t *sequence,
+ uint32_t *sequence,
uint32_t *native_type);
extern void i915_poke_flush(struct drm_device *dev, uint32_t class);
extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags);
struct drm_mem_type_manager *man);
extern uint32_t i915_evict_mask(struct drm_buffer_object *bo);
extern int i915_move(struct drm_buffer_object *bo, int evict,
- int no_wait, struct drm_bo_mem_reg *new_mem);
+ int no_wait, struct drm_bo_mem_reg *new_mem);
void i915_flush_ttm(struct drm_ttm *ttm);
#endif
#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
-#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
+#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
#define I915_VERBOSE 0
#define VGA_CR_INDEX_CGA 0x3d4
#define VGA_CR_DATA_CGA 0x3d5
-#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
+#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
#define CMD_REPORT_HEAD (7<<23)
#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
#define I915REG_HWSTAM 0x02098
#define I915REG_INT_IDENTITY_R 0x020a4
-#define I915REG_INT_MASK_R 0x020a8
+#define I915REG_INT_MASK_R 0x020a8
#define I915REG_INT_ENABLE_R 0x020a0
#define I915REG_INSTPM 0x020c0
#define SRX_INDEX 0x3c4
#define SRX_DATA 0x3c5
#define SR01 1
-#define SR01_SCREEN_OFF (1<<5)
+#define SR01_SCREEN_OFF (1<<5)
#define PPCR 0x61204
#define PPCR_ON (1<<0)
#define ADPA_DPMS_OFF (3<<10)
#define NOPID 0x2094
-#define LP_RING 0x2030
-#define HP_RING 0x2040
+#define LP_RING 0x2030
+#define HP_RING 0x2040
/* The binner has its own ring buffer:
*/
#define HWB_RING 0x2400
-#define RING_TAIL 0x00
+#define RING_TAIL 0x00
#define TAIL_ADDR 0x001FFFF8
-#define RING_HEAD 0x04
-#define HEAD_WRAP_COUNT 0xFFE00000
-#define HEAD_WRAP_ONE 0x00200000
-#define HEAD_ADDR 0x001FFFFC
-#define RING_START 0x08
-#define START_ADDR 0x0xFFFFF000
-#define RING_LEN 0x0C
-#define RING_NR_PAGES 0x001FF000
-#define RING_REPORT_MASK 0x00000006
-#define RING_REPORT_64K 0x00000002
-#define RING_REPORT_128K 0x00000004
-#define RING_NO_REPORT 0x00000000
-#define RING_VALID_MASK 0x00000001
-#define RING_VALID 0x00000001
-#define RING_INVALID 0x00000000
+#define RING_HEAD 0x04
+#define HEAD_WRAP_COUNT 0xFFE00000
+#define HEAD_WRAP_ONE 0x00200000
+#define HEAD_ADDR 0x001FFFFC
+#define RING_START 0x08
+#define START_ADDR 0x0xFFFFF000
+#define RING_LEN 0x0C
+#define RING_NR_PAGES 0x001FF000
+#define RING_REPORT_MASK 0x00000006
+#define RING_REPORT_64K 0x00000002
+#define RING_REPORT_128K 0x00000004
+#define RING_NO_REPORT 0x00000000
+#define RING_VALID_MASK 0x00000001
+#define RING_VALID 0x00000001
+#define RING_INVALID 0x00000000
/* Instruction parser error reg:
*/
*/
#define DMA_FADD_S 0x20d4
-/* Cache mode 0 reg.
+/* Cache mode 0 reg.
* - Manipulating render cache behaviour is central
* to the concept of zone rendering, tuning this reg can help avoid
* unnecessary render cache reads and even writes (for z/stencil)
#define BINCTL 0x2420
#define BC_MASK (1 << 9)
-/* Binned scene info.
+/* Binned scene info.
*/
#define BINSCENE 0x2428
#define BS_OP_LOAD (1 << 8)
*/
#define BDCD 0x2488
-/* Binner pointer cache debug reg:
+/* Binner pointer cache debug reg:
*/
#define BPCD 0x248c
#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
-#define MI_BATCH_BUFFER ((0x30<<23)|1)
-#define MI_BATCH_BUFFER_START (0x31<<23)
-#define MI_BATCH_BUFFER_END (0xA<<23)
+#define MI_BATCH_BUFFER ((0x30<<23)|1)
+#define MI_BATCH_BUFFER_START (0x31<<23)
+#define MI_BATCH_BUFFER_END (0xA<<23)
#define MI_BATCH_NON_SECURE (1)
#define MI_BATCH_NON_SECURE_I965 (1<<8)
/* I830 CRTC registers */
#define HTOTAL_A 0x60000
#define HBLANK_A 0x60004
-#define HSYNC_A 0x60008
+#define HSYNC_A 0x60008
#define VTOTAL_A 0x6000c
#define VBLANK_A 0x60010
-#define VSYNC_A 0x60014
+#define VSYNC_A 0x60014
#define PIPEASRC 0x6001c
#define BCLRPAT_A 0x60020
#define VSYNCSHIFT_A 0x60028
#define HTOTAL_B 0x61000
#define HBLANK_B 0x61004
-#define HSYNC_B 0x61008
+#define HSYNC_B 0x61008
#define VTOTAL_B 0x6100c
#define VBLANK_B 0x61010
-#define VSYNC_B 0x61014
+#define VSYNC_B 0x61014
#define PIPEBSRC 0x6101c
#define BCLRPAT_B 0x61020
#define VSYNCSHIFT_B 0x61028
*/
# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
-/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
+/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
* This best be set to the default value (3) or the CRT won't work. No,
* I don't entirely understand what this does...
*/
# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
#define ADPA 0x61100
-#define ADPA_DAC_ENABLE (1<<31)
+#define ADPA_DAC_ENABLE (1<<31)
#define ADPA_DAC_DISABLE 0
#define ADPA_PIPE_SELECT_MASK (1<<30)
#define ADPA_PIPE_A_SELECT 0
#define PIPEACONF_PIPE_UNLOCKED 0
#define PIPEACONF_PIPE_LOCKED (1<<25)
#define PIPEACONF_PALETTE 0
-#define PIPEACONF_GAMMA (1<<24)
+#define PIPEACONF_GAMMA (1<<24)
#define PIPECONF_FORCE_BORDER (1<<25)
#define PIPECONF_PROGRESSIVE (0 << 21)
#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
#define PIPEBCONF_DISABLE 0
#define PIPEBCONF_DOUBLE_WIDE (1<<30)
#define PIPEBCONF_DISABLE 0
-#define PIPEBCONF_GAMMA (1<<24)
+#define PIPEBCONF_GAMMA (1<<24)
#define PIPEBCONF_PALETTE 0
#define PIPEBGCMAXRED 0x71010
#define DSPACNTR 0x70180
#define DSPBCNTR 0x71180
-#define DISPLAY_PLANE_ENABLE (1<<31)
+#define DISPLAY_PLANE_ENABLE (1<<31)
#define DISPLAY_PLANE_DISABLE 0
#define DISPPLANE_GAMMA_ENABLE (1<<30)
#define DISPPLANE_GAMMA_DISABLE 0
#define DISPPLANE_8BPP (0x2<<26)
#define DISPPLANE_15_16BPP (0x4<<26)
#define DISPPLANE_16BPP (0x5<<26)
-#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
+#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
#define DISPPLANE_32BPP (0x7<<26)
#define DISPPLANE_STEREO_ENABLE (1<<25)
#define DISPPLANE_STEREO_DISABLE 0
#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
- (dev)->pci_device == 0x29B2 || \
+ (dev)->pci_device == 0x29B2 || \
(dev)->pci_device == 0x29D2)
#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
/*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
+ *
*/
#include "drmP.h"
pipea_stats = I915_READ(I915REG_PIPEASTAT);
pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
-
+
temp = I915_READ16(I915REG_INT_IDENTITY_R);
temp &= (dev_priv->irq_enable_reg | USER_INT_FLAG);
if (dev_priv->swaps_pending > 0)
drm_locked_tasklet(dev, i915_vblank_tasklet);
- I915_WRITE(I915REG_PIPEASTAT,
+ I915_WRITE(I915REG_PIPEASTAT,
pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
I915_VBLANK_CLEAR);
I915_WRITE(I915REG_PIPEBSTAT,
int i915_emit_irq(struct drm_device * dev)
{
-
+
drm_i915_private_t *dev_priv = dev->dev_private;
RING_LOCALS;
DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
}
-
+
void i915_user_irq_off(drm_i915_private_t *dev_priv)
{
DRM_SPINLOCK(&dev_priv->user_irq_lock);
}
DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
}
-
+
static int i915_wait_irq(struct drm_device * dev, int irq_nr)
{
return 0;
dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
-
+
i915_user_irq_on(dev_priv);
DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
READ_BREADCRUMB(dev_priv) >= irq_nr);
DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
(((cur_vblank = atomic_read(counter))
- *sequence) <= (1<<23)));
-
+
*sequence = cur_vblank;
return ret;
static void i915_enable_interrupt (struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-
- dev_priv->irq_enable_reg = USER_INT_FLAG;
+
+ dev_priv->irq_enable_reg = USER_INT_FLAG;
if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
dev_priv->irq_enable_reg |= VSYNC_PIPEA_FLAG;
if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
}
if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
- DRM_ERROR("%s called with invalid pipe 0x%x\n",
+ DRM_ERROR("%s called with invalid pipe 0x%x\n",
__FUNCTION__, pipe->pipe);
return -EINVAL;
}
DRM_ERROR("get_heap failed");
return -EFAULT;
}
-
+
if (!*heap) {
DRM_ERROR("heap not initialized?");
return -EFAULT;
*
* \param dev_priv pointer to device private data structure.
* \param entries number of free entries in the FIFO to wait for.
- *
+ *
* \returns zero on success, or -EBUSY if the timeout (specificed by
* drm_mach64_private::usec_timeout) occurs.
*/
*
* This function should be called before writing new entries to the ring
* buffer.
- *
+ *
* \param dev_priv pointer to device private data structure.
* \param n number of free entries in the ring buffer to wait for.
- *
+ *
* \returns zero on success, or -EBUSY if the timeout (specificed by
* drm_mach64_private_t::usec_timeout) occurs.
*
}
/**
- * Wait until all DMA requests have been processed...
+ * Wait until all DMA requests have been processed...
*
* \sa mach64_wait_ring()
*/
#define MACH64_AGP_CNTL 0x014c
#define MACH64_ALPHA_TST_CNTL 0x0550
-#define MACH64_DSP_CONFIG 0x0420
-#define MACH64_DSP_ON_OFF 0x0424
-#define MACH64_EXT_MEM_CNTL 0x04ac
-#define MACH64_GEN_TEST_CNTL 0x04d0
-#define MACH64_HW_DEBUG 0x047c
-#define MACH64_MEM_ADDR_CONFIG 0x0434
-#define MACH64_MEM_BUF_CNTL 0x042c
-#define MACH64_MEM_CNTL 0x04b0
+#define MACH64_DSP_CONFIG 0x0420
+#define MACH64_DSP_ON_OFF 0x0424
+#define MACH64_EXT_MEM_CNTL 0x04ac
+#define MACH64_GEN_TEST_CNTL 0x04d0
+#define MACH64_HW_DEBUG 0x047c
+#define MACH64_MEM_ADDR_CONFIG 0x0434
+#define MACH64_MEM_BUF_CNTL 0x042c
+#define MACH64_MEM_CNTL 0x04b0
#define MACH64_BM_ADDR 0x0648
#define MACH64_BM_COMMAND 0x0188
#define MACH64_CLR_CMP_CLR 0x0700
#define MACH64_CLR_CMP_CNTL 0x0708
#define MACH64_CLR_CMP_MASK 0x0704
-#define MACH64_CONFIG_CHIP_ID 0x04e0
-#define MACH64_CONFIG_CNTL 0x04dc
-#define MACH64_CONFIG_STAT0 0x04e4
-#define MACH64_CONFIG_STAT1 0x0494
-#define MACH64_CONFIG_STAT2 0x0498
+#define MACH64_CONFIG_CHIP_ID 0x04e0
+#define MACH64_CONFIG_CNTL 0x04dc
+#define MACH64_CONFIG_STAT0 0x04e4
+#define MACH64_CONFIG_STAT1 0x0494
+#define MACH64_CONFIG_STAT2 0x0498
#define MACH64_CONTEXT_LOAD_CNTL 0x072c
#define MACH64_CONTEXT_MASK 0x0720
#define MACH64_COMPOSITE_SHADOW_ID 0x0798
-#define MACH64_CRC_SIG 0x04e8
-#define MACH64_CUSTOM_MACRO_CNTL 0x04d4
+#define MACH64_CRC_SIG 0x04e8
+#define MACH64_CUSTOM_MACRO_CNTL 0x04d4
#define MACH64_DP_BKGD_CLR 0x06c0
#define MACH64_DP_FOG_CLR 0x06c4
#define MACH64_TEX_0_OFF 0x05c0
#define MACH64_TEX_CNTL 0x0774
#define MACH64_TEX_SIZE_PITCH 0x0770
-#define MACH64_TIMER_CONFIG 0x0428
+#define MACH64_TIMER_CONFIG 0x0428
#define MACH64_VERTEX_1_ARGB 0x0254
#define MACH64_VERTEX_1_S 0x0240
#define RING_WRITE_OFS _ring_write
-#define BEGIN_RING( n ) \
+#define BEGIN_RING( n ) \
do { \
if ( MACH64_VERBOSE ) { \
DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
_ring_write &= _ring_mask; \
} while (0)
-#define ADVANCE_RING() \
+#define ADVANCE_RING() \
do { \
if ( MACH64_VERBOSE ) { \
DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
#define DMALOCALS \
drm_mach64_freelist_t *_entry = NULL; \
- struct drm_buf *_buf = NULL; \
+ struct drm_buf *_buf = NULL; \
u32 *_buf_wptr; int _outcount
#define GETBUFPTR( __buf ) \
-((dev_priv->is_pci) ? \
- ((u32 *)(__buf)->address) : \
+((dev_priv->is_pci) ? \
+ ((u32 *)(__buf)->address) : \
((u32 *)((char *)dev_priv->dev_buffers->handle + (__buf)->offset)))
#define GETBUFADDR( __buf ) ((u32)(__buf)->bus_address)
return 0;
}
-#define DMASETPTR( _p ) \
+#define DMASETPTR( _p ) \
do { \
_buf = (_p); \
_outcount = 0; \
__FUNCTION__, _buf->idx ); \
return -EFAULT; \
} \
- } else { \
+ } else { \
if (list_empty(&dev_priv->placeholders)) { \
DRM_ERROR( "DMAADVANCE() in %s: empty placeholder list\n", \
- __FUNCTION__ ); \
+ __FUNCTION__ ); \
return -EFAULT; \
} \
ptr = dev_priv->placeholders.next; \
/**
* \file mga_dma.c
* DMA support for MGA G200 / G400.
- *
+ *
* \author Rickard E. (Rik) Faith <faith@valinux.com>
* \author Jeff Hartmann <jhartmann@valinux.com>
* \author Keith Whitwell <keith@tungstengraphics.com>
/**
* Bootstrap the driver for AGP DMA.
- *
+ *
* \todo
* Investigate whether there is any benifit to storing the WARP microcode in
* AGP memory. If not, the microcode may as well always be put in PCI
/**
* Bootstrap the driver for PCI DMA.
- *
+ *
* \todo
* The algorithm for decreasing the size of the primary DMA buffer could be
* better. The size should be rounded up to the nearest page size, then
* \todo
* Determine whether the maximum address passed to drm_pci_alloc is correct.
* The same goes for drm_addbufs_pci.
- *
+ *
* \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
*/
static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
int err;
struct drm_buf_desc req;
-
+
if (dev->dma == NULL) {
DRM_ERROR("dev->dma is NULL\n");
return -EFAULT;
if (dev_priv->primary->size != dma_bs->primary_size) {
DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
- dma_bs->primary_size,
+ dma_bs->primary_size,
(unsigned) dev_priv->primary->size);
dma_bs->primary_size = dev_priv->primary->size;
}
for ( bin_count = dma_bs->secondary_bin_count
- ; bin_count > 0
+ ; bin_count > 0
; bin_count-- ) {
(void) memset( &req, 0, sizeof(req) );
req.count = bin_count;
break;
}
}
-
+
if (bin_count == 0) {
DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
return err;
if (is_agp) {
err = mga_do_agp_dma_bootstrap(dev, dma_bs);
}
-
+
/* If we attempted to initialize the card for AGP DMA but failed,
* clean-up any mess that may have been created.
*/
drm_mga_dma_bootstrap_t *bootstrap = data;
int err;
static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
- const drm_mga_private_t * const dev_priv =
+ const drm_mga_private_t * const dev_priv =
(drm_mga_private_t *) dev->dev_private;
&& (dev_priv->warp->type != _DRM_CONSISTENT))
drm_core_ioremapfree(dev_priv->warp, dev);
- if ((dev_priv->primary != NULL)
+ if ((dev_priv->primary != NULL)
&& (dev_priv->primary->type != _DRM_CONSISTENT))
drm_core_ioremapfree(dev_priv->primary, dev);
typedef struct drm_mga_dma_bootstrap {
/**
* \name AGP texture region
- *
+ *
* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
* be filled in with the actual AGP texture settings.
- *
+ *
* \warning
* If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
* is zero, it means that PCI memory (most likely through the use of
/**
* Requested size of the primary DMA region.
- *
+ *
* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
* filled in with the actual AGP mode. If AGP was not available
*/
/**
* Requested number of secondary DMA buffers.
- *
+ *
* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
* filled in with the actual number of secondary DMA buffers
* allocated. Particularly when PCI DMA is used, this may be
* (subtantially) less than the number requested.
*/
uint32_t secondary_bin_count;
-
-
+
+
/**
* Requested size of each secondary DMA buffer.
- *
+ *
* While the kernel \b is free to reduce
* dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
* to reduce dma_mga_dma_bootstrap::secondary_bin_size.
* \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
* zero, it means that PCI DMA should be used, even if AGP is
* possible.
- *
+ *
* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
* filled in with the actual AGP mode. If AGP was not available
* (i.e., PCI DMA was used), this value will be zero.
/**
* \name MMIO region parameters.
- *
+ *
* \sa drm_mga_private_t::mmio
*/
/*@{*/
drm_local_map_t *warp;
drm_local_map_t *primary;
drm_local_map_t *agp_textures;
-
+
unsigned long agp_handle;
unsigned int agp_size;
} drm_mga_private_t;
#define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val))
#endif
-#define DWGREG0 0x1c00
-#define DWGREG0_END 0x1dff
+#define DWGREG0 0x1c00
+#define DWGREG0_END 0x1dff
#define DWGREG1 0x2c00
#define DWGREG1_END 0x2dff
#define MGA_VINTCLR (1 << 4)
#define MGA_VINTEN (1 << 5)
-#define MGA_ALPHACTRL 0x2c7c
-#define MGA_AR0 0x1c60
-#define MGA_AR1 0x1c64
-#define MGA_AR2 0x1c68
-#define MGA_AR3 0x1c6c
-#define MGA_AR4 0x1c70
-#define MGA_AR5 0x1c74
-#define MGA_AR6 0x1c78
+#define MGA_ALPHACTRL 0x2c7c
+#define MGA_AR0 0x1c60
+#define MGA_AR1 0x1c64
+#define MGA_AR2 0x1c68
+#define MGA_AR3 0x1c6c
+#define MGA_AR4 0x1c70
+#define MGA_AR5 0x1c74
+#define MGA_AR6 0x1c78
#define MGA_CXBNDRY 0x1c80
-#define MGA_CXLEFT 0x1ca0
+#define MGA_CXLEFT 0x1ca0
#define MGA_CXRIGHT 0x1ca4
-#define MGA_DMAPAD 0x1c54
-#define MGA_DSTORG 0x2cb8
-#define MGA_DWGCTL 0x1c00
+#define MGA_DMAPAD 0x1c54
+#define MGA_DSTORG 0x2cb8
+#define MGA_DWGCTL 0x1c00
# define MGA_OPCOD_MASK (15 << 0)
# define MGA_OPCOD_TRAP (4 << 0)
# define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
# define MGA_CLIPDIS (1 << 31)
#define MGA_DWGSYNC 0x2c4c
-#define MGA_FCOL 0x1c24
-#define MGA_FIFOSTATUS 0x1e10
-#define MGA_FOGCOL 0x1cf4
+#define MGA_FCOL 0x1c24
+#define MGA_FIFOSTATUS 0x1e10
+#define MGA_FOGCOL 0x1cf4
#define MGA_FXBNDRY 0x1c84
-#define MGA_FXLEFT 0x1ca8
+#define MGA_FXLEFT 0x1ca8
#define MGA_FXRIGHT 0x1cac
-#define MGA_ICLEAR 0x1e18
+#define MGA_ICLEAR 0x1e18
# define MGA_SOFTRAPICLR (1 << 0)
# define MGA_VLINEICLR (1 << 5)
-#define MGA_IEN 0x1e1c
+#define MGA_IEN 0x1e1c
# define MGA_SOFTRAPIEN (1 << 0)
# define MGA_VLINEIEN (1 << 5)
-#define MGA_LEN 0x1c5c
+#define MGA_LEN 0x1c5c
#define MGA_MACCESS 0x1c04
-#define MGA_PITCH 0x1c8c
-#define MGA_PLNWT 0x1c1c
-#define MGA_PRIMADDRESS 0x1e58
+#define MGA_PITCH 0x1c8c
+#define MGA_PLNWT 0x1c1c
+#define MGA_PRIMADDRESS 0x1e58
# define MGA_DMA_GENERAL (0 << 0)
# define MGA_DMA_BLIT (1 << 0)
# define MGA_DMA_VECTOR (2 << 0)
# define MGA_PRIMPTREN0 (1 << 0)
# define MGA_PRIMPTREN1 (1 << 1)
-#define MGA_RST 0x1e40
+#define MGA_RST 0x1e40
# define MGA_SOFTRESET (1 << 0)
# define MGA_SOFTEXTRST (1 << 1)
-#define MGA_SECADDRESS 0x2c40
-#define MGA_SECEND 0x2c44
-#define MGA_SETUPADDRESS 0x2cd0
-#define MGA_SETUPEND 0x2cd4
+#define MGA_SECADDRESS 0x2c40
+#define MGA_SECEND 0x2c44
+#define MGA_SETUPADDRESS 0x2cd0
+#define MGA_SETUPEND 0x2cd4
#define MGA_SGN 0x1c58
#define MGA_SOFTRAP 0x2c48
-#define MGA_SRCORG 0x2cb4
+#define MGA_SRCORG 0x2cb4
# define MGA_SRMMAP_MASK (1 << 0)
# define MGA_SRCMAP_FB (0 << 0)
# define MGA_SRCMAP_SYSMEM (1 << 0)
# define MGA_SRCACC_MASK (1 << 1)
# define MGA_SRCACC_PCI (0 << 1)
# define MGA_SRCACC_AGP (1 << 1)
-#define MGA_STATUS 0x1e14
+#define MGA_STATUS 0x1e14
# define MGA_SOFTRAPEN (1 << 0)
# define MGA_VSYNCPEN (1 << 4)
# define MGA_VLINEPEN (1 << 5)
# define MGA_DWGENGSTS (1 << 16)
# define MGA_ENDPRDMASTS (1 << 17)
#define MGA_STENCIL 0x2cc8
-#define MGA_STENCILCTL 0x2ccc
+#define MGA_STENCILCTL 0x2ccc
-#define MGA_TDUALSTAGE0 0x2cf8
-#define MGA_TDUALSTAGE1 0x2cfc
-#define MGA_TEXBORDERCOL 0x2c5c
-#define MGA_TEXCTL 0x2c30
+#define MGA_TDUALSTAGE0 0x2cf8
+#define MGA_TDUALSTAGE1 0x2cfc
+#define MGA_TEXBORDERCOL 0x2c5c
+#define MGA_TEXCTL 0x2c30
#define MGA_TEXCTL2 0x2c3c
# define MGA_DUALTEX (1 << 7)
# define MGA_G400_TC2_MAGIC (1 << 15)
# define MGA_MAP1_ENABLE (1 << 31)
-#define MGA_TEXFILTER 0x2c58
-#define MGA_TEXHEIGHT 0x2c2c
-#define MGA_TEXORG 0x2c24
+#define MGA_TEXFILTER 0x2c58
+#define MGA_TEXHEIGHT 0x2c2c
+#define MGA_TEXORG 0x2c24
# define MGA_TEXORGMAP_MASK (1 << 0)
# define MGA_TEXORGMAP_FB (0 << 0)
# define MGA_TEXORGMAP_SYSMEM (1 << 0)
#define MGA_TEXORG2 0x2ca8
#define MGA_TEXORG3 0x2cac
#define MGA_TEXORG4 0x2cb0
-#define MGA_TEXTRANS 0x2c34
-#define MGA_TEXTRANSHIGH 0x2c38
-#define MGA_TEXWIDTH 0x2c28
-
-#define MGA_WACCEPTSEQ 0x1dd4
-#define MGA_WCODEADDR 0x1e6c
-#define MGA_WFLAG 0x1dc4
-#define MGA_WFLAG1 0x1de0
+#define MGA_TEXTRANS 0x2c34
+#define MGA_TEXTRANSHIGH 0x2c38
+#define MGA_TEXWIDTH 0x2c28
+
+#define MGA_WACCEPTSEQ 0x1dd4
+#define MGA_WCODEADDR 0x1e6c
+#define MGA_WFLAG 0x1dc4
+#define MGA_WFLAG1 0x1de0
#define MGA_WFLAGNB 0x1e64
-#define MGA_WFLAGNB1 0x1e08
+#define MGA_WFLAGNB1 0x1e08
#define MGA_WGETMSB 0x1dc8
-#define MGA_WIADDR 0x1dc0
+#define MGA_WIADDR 0x1dc0
#define MGA_WIADDR2 0x1dd8
# define MGA_WMODE_SUSPEND (0 << 0)
# define MGA_WMODE_RESUME (1 << 0)
# define MGA_WMODE_JUMP (2 << 0)
# define MGA_WMODE_START (3 << 0)
# define MGA_WAGP_ENABLE (1 << 2)
-#define MGA_WMISC 0x1e70
+#define MGA_WMISC 0x1e70
# define MGA_WUCODECACHE_ENABLE (1 << 0)
# define MGA_WMASTER_ENABLE (1 << 1)
# define MGA_WCACHEFLUSH_ENABLE (1 << 3)
#define MGA_WVRTXSZ 0x1dcc
-#define MGA_YBOT 0x1c9c
-#define MGA_YDST 0x1c90
+#define MGA_YBOT 0x1c9c
+#define MGA_YDST 0x1c90
#define MGA_YDSTLEN 0x1c88
#define MGA_YDSTORG 0x1c94
-#define MGA_YTOP 0x1c98
+#define MGA_YTOP 0x1c98
-#define MGA_ZORG 0x1c0c
+#define MGA_ZORG 0x1c0c
/* This finishes the current batch of commands
*/
-#define MGA_EXEC 0x0100
+#define MGA_EXEC 0x0100
/* AGP PLL encoding (for G200 only).
*/
-#define MGA_AGP_PLL 0x1e4c
+#define MGA_AGP_PLL 0x1e4c
# define MGA_AGP2XPLL_DISABLE (0 << 0)
# define MGA_AGP2XPLL_ENABLE (1 << 0)
/* Disable *all* interrupts */
MGA_WRITE(MGA_IEN, 0);
-
+
dev->irq_enabled = 0;
}
drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
DMA_LOCALS;
-/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
-/* tex->texctl, tex->texctl2); */
+/* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
+/* tex->texctl, tex->texctl2); */
BEGIN_DMA(6);
drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
DMA_LOCALS;
-/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
-/* tex->texctl, tex->texctl2); */
+/* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */
+/* tex->texctl, tex->texctl2); */
BEGIN_DMA(5);
unsigned int pipe = sarea_priv->warp_pipe;
DMA_LOCALS;
-/* printk("mga_g400_emit_pipe %x\n", pipe); */
+/* printk("mga_g400_emit_pipe %x\n", pipe); */
BEGIN_DMA(10);
#define DRM_NOUVEAU_MEM_FREE 0x09
#endif /* __NOUVEAU_DRM_H__ */
-
};
#define NVOBJ_ENGINE_SW 0
-#define NVOBJ_ENGINE_GR 1
+#define NVOBJ_ENGINE_GR 1
#define NVOBJ_ENGINE_INT 0xdeadbeef
#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
#define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
#endif /* __NOUVEAU_DRV_H__ */
-
-/*
+/*
* Copyright 2005-2006 Stephane Marchesin
* All Rights Reserved.
*
/* voir nv_xaa.c : NVResetGraphics
* mémoire mappée par nv_driver.c : NVMapMem
- * voir nv_driver.c : NVPreInit
+ * voir nv_driver.c : NVPreInit
*/
static int nouveau_fifo_instmem_configure(struct drm_device *dev)
struct drm_nouveau_private *dev_priv = dev->dev_private;
NV_WRITE(NV03_PFIFO_RAMHT,
- (0x03 << 24) /* search 128 */ |
+ (0x03 << 24) /* search 128 */ |
((dev_priv->ramht_bits - 9) << 16) |
(dev_priv->ramht_offset >> 8)
);
NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACHE1_BIG_ENDIAN |
-#endif
+#endif
0x00000000);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
/*
* Alright, here is the full story
- * Nvidia cards have multiple hw fifo contexts (praise them for that,
+ * Nvidia cards have multiple hw fifo contexts (praise them for that,
* no complicated crash-prone context switches)
- * We allocate a new context for each app and let it write to it directly
+ * We allocate a new context for each app and let it write to it directly
* (woo, full userspace command submission !)
* When there are no more contexts, you lost
*/
if (status & NV_PFIFO_INTR_CACHE_ERROR) {
uint32_t mthd, data;
int ptr;
-
+
ptr = get >> 2;
if (dev_priv->card_type < NV_40) {
mthd = NV_READ(NV04_PFIFO_CACHE1_METHOD(ptr));
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t chid;
-
+
chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1);
DRM_DEBUG("PGRAPH context switch interrupt channel %x\n", chid);
return IRQ_HANDLED;
}
-
return 0;
}
-/*
+/*
* Free all blocks associated with the releasing file_priv
*/
void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap)
}
}
-/*
+/*
* Cleanup everything
*/
void nouveau_mem_takedown(struct mem_block **heap)
} else {
uint64_t mem;
- mem = (NV_READ(NV04_FIFO_DATA) &
+ mem = (NV_READ(NV04_FIFO_DATA) &
NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >>
NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT;
return mem*1024*1024;
DRM_DEBUG("Available VRAM: %dKiB\n", fb_size>>10);
if (fb_size>256*1024*1024) {
- /* On cards with > 256Mb, you can't map everything.
+ /* On cards with > 256Mb, you can't map everything.
* So we create a second FB heap for that type of memory */
if (nouveau_mem_init_heap(&dev_priv->fb_heap,
0, 256*1024*1024))
if (!ret) {
ret = nouveau_sgdma_nottm_hack_init(dev);
if (ret)
- nouveau_sgdma_takedown(dev);
+ nouveau_sgdma_takedown(dev);
}
if (ret)
0, dev_priv->gart_info.aper_size)) {
if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) {
nouveau_sgdma_nottm_hack_takedown(dev);
- nouveau_sgdma_takedown(dev);
+ nouveau_sgdma_takedown(dev);
}
}
}
} else {
if (nouveau_mem_init_heap(&dev_priv->pci_heap, 0,
dev->sg->pages * PAGE_SIZE)) {
- DRM_ERROR("Unable to initialize pci_heap!");
+ DRM_ERROR("Unable to initialize pci_heap!");
}
}
}
int type;
struct drm_nouveau_private *dev_priv = dev->dev_private;
- /*
- * Make things easier on ourselves: all allocations are page-aligned.
+ /*
+ * Make things easier on ourselves: all allocations are page-aligned.
* We need that to map allocated regions into the user space
*/
if (alignment < PAGE_SHIFT)
ret = drm_addmap(dev, block->start, block->size,
_DRM_SCATTER_GATHER, 0, &block->map);
- if (ret) {
+ if (ret) {
nouveau_mem_free_block(block);
return NULL;
}
nouveau_mem_free(dev, block);
return 0;
}
-
-
} else {
target = NV_DMA_TARGET_AGP;
}
- } else
+ } else
if (chan->notifier_block->flags & NOUVEAU_MEM_PCI) {
target = NV_DMA_TARGET_PCI_NONLINEAR;
} else {
return 0;
}
-
struct nouveau_gpuobj_ref *ref;
struct list_head *entry, *tmp;
- list_for_each_safe(entry, tmp, &chan->ramht_refs) {
+ list_for_each_safe(entry, tmp, &chan->ramht_refs) {
ref = list_entry(entry, struct nouveau_gpuobj_ref, list);
if (ref->handle == handle) {
DMA objects are used to reference a piece of memory in the
framebuffer, PCI or AGP address space. Each object is 16 bytes big
and looks as follows:
-
+
entry[0]
11:0 class (seems like I can always use 0 here)
12 page table present?
struct drm_nouveau_private *dev_priv = dev->dev_private;
int ret;
uint32_t is_scatter_gather = 0;
-
+
/* Total number of pages covered by the request.
*/
const unsigned int page_count = (size + PAGE_SIZE - 1) / PAGE_SIZE;
default:
break;
}
-
+
ret = nouveau_gpuobj_new(dev, chan,
is_scatter_gather ? ((page_count << 2) + 12) : nouveau_gpuobj_class_instmem_size(dev, class),
16,
adjust = offset & 0x00000fff;
if (access != NV_DMA_ACCESS_RO)
pte_flags |= (1<<1);
-
- if ( ! is_scatter_gather )
+
+ if ( ! is_scatter_gather )
{
frame = offset & ~0x00000fff;
-
+
INSTANCE_WR(*gpuobj, 0, ((1<<12) | (1<<13) |
(adjust << 20) |
(access << 14) |
INSTANCE_WR(*gpuobj, 2, frame | pte_flags);
INSTANCE_WR(*gpuobj, 3, frame | pte_flags);
}
- else
+ else
{
/* Intial page entry in the scatter-gather area that
* corresponds to the base offset
/*write starting at the third dword*/
instance_offset = 2;
-
+
/*for each PAGE, get its bus address, fill in the page table entry, and advance*/
for (i = 0; i < page_count; i++) {
if (dev->sg->busaddr[idx] == 0) {
}
frame = (uint32_t) dev->sg->busaddr[idx];
- INSTANCE_WR(*gpuobj, instance_offset,
+ INSTANCE_WR(*gpuobj, instance_offset,
frame | pte_flags);
-
+
idx++;
instance_offset ++;
- }
+ }
}
} else {
uint32_t flags0, flags5;
entry[0]:
11:0 class (maybe uses more bits here?)
17 user clip enable
- 21:19 patch config
+ 21:19 patch config
25 patch status valid ?
entry[1]:
15:0 DMA notifier (maybe 20:0)
/* NV50 VM, point offset 0-512MiB at shared PCIEGART table */
if (dev_priv->card_type >= NV_50) {
uint32_t vm_offset;
-
+
vm_offset = (dev_priv->chipset & 0xf0) == 0x50 ? 0x1400 : 0x200;
vm_offset += chan->ramin->gpuobj->im_pramin->start;
if ((ret = nouveau_gpuobj_new_fake(dev, vm_offset, ~0, 0x4000,
DRM_DEBUG("ch%d\n", chan->id);
- list_for_each_safe(entry, tmp, &chan->ramht_refs) {
+ list_for_each_safe(entry, tmp, &chan->ramht_refs) {
ref = list_entry(entry, struct nouveau_gpuobj_ref, list);
nouveau_gpuobj_ref_del(dev, &ref);
NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(init->channel, file_priv, chan);
//FIXME: check args, only allow trusted objects to be created
-
+
if (init->handle == ~0)
return -EINVAL;
return 0;
}
-
#define NV40_RAMFC_UNK_48 0x48
#define NV40_RAMFC_UNK_4C 0x4C
#define NV40_RAMFC_UNK_50 0x50
-
-/*
+/*
* Copyright 2005 Stephane Marchesin
* All Rights Reserved.
*
/* map the mmio regs */
ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
- drm_get_resource_len(dev, 0),
+ drm_get_resource_len(dev, 0),
_DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
if (ret) {
DRM_ERROR("Unable to initialize the mmio mapping (%d). "
DRM_DEBUG("vendor: 0x%X device: 0x%X class: 0x%X\n", dev->pci_vendor, dev->pci_device, dev->pdev->class);
/* Time to determine the card architecture */
- regs = ioremap_nocache(pci_resource_start(dev->pdev, 0), 0x8);
+ regs = ioremap_nocache(pci_resource_start(dev->pdev, 0), 0x8);
if (!regs) {
DRM_ERROR("Could not ioremap to determine register\n");
return -ENOMEM;
case NOUVEAU_GETPARAM_PCI_PHYSICAL:
if ( dev -> sg )
getparam->value=(uint64_t) dev->sg->virtual;
- else
+ else
{
DRM_ERROR("Requested PCIGART address, while no PCIGART was created\n");
return -EINVAL;
}
}
}
-
-
*/
int nouveau_sw_method_execute(struct drm_device *dev, uint32_t oclass, uint32_t method); /* execute the given software method, returns 0 on success */
-
nv04_fb_takedown(struct drm_device *dev)
{
}
-
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
-
+
NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
nouveau_gpuobj_ref_del(dev, &chan->ramfc);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET));
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT));
-
+
tmp = RAMFC_RD(DMA_INSTANCE);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
-
+
NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, RAMFC_RD(DMA_STATE));
NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, RAMFC_RD(DMA_FETCH));
NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, RAMFC_RD(ENGINE));
RAMFC_WR(DMA_FETCH, NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE));
RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1));
-
+
return 0;
}
-
-/*
+/*
* Copyright 2007 Stephane Marchesin
* All Rights Reserved.
*
if (gpuobj->im_bound)
dev_priv->Engine.instmem.unbind(dev, gpuobj);
gpuobj->im_backing = NULL;
- }
+ }
}
int
gpuobj->im_bound = 0;
return 0;
}
-
nv04_mc_takedown(struct drm_device *dev)
{
}
-
nv04_timer_takedown(struct drm_device *dev)
{
}
-
nv10_fb_takedown(struct drm_device *dev)
{
}
-
-/*
+/*
* Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
* All Rights Reserved.
*
if (last) {
nouveau_wait_for_idle(dev);
nv10_graph_save_context(last);
- }
+ }
nouveau_wait_for_idle(dev);
void nv10_graph_takedown(struct drm_device *dev)
{
}
-
nv40_fb_takedown(struct drm_device *dev)
{
}
-
NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
return 0;
}
-
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
int i;
-
+
INSTANCE_WR(ctx, 0x00000/4, ctx->im_pramin->start);
INSTANCE_WR(ctx, 0x00024/4, 0x0000ffff);
INSTANCE_WR(ctx, 0x00028/4, 0x0000ffff);
tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
NV_WRITE(NV40_PGRAPH_CTXCTL_0310, tmp);
-
+
tmp = NV_READ(NV40_PGRAPH_CTXCTL_0304);
tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
NV_WRITE(NV40_PGRAPH_CTXCTL_0304, tmp);
static uint32_t nv4a_ctx_voodoo[] = {
- 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
- 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409965, 0x00409e06,
- 0x0040ac68, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
- 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061,
- 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,
- 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,
- 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,
- 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,
- 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,
- 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407de6, 0x002000f1,
- 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b,
- 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6,
- 0x001646cc, 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700,
- 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003,
- 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200232, 0x0060000a,
- 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940,
- 0x00140965, 0x00148a00, 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00,
- 0x0010cd04, 0x0010cd08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00,
- 0x00104f06, 0x002002c8, 0x0060000a, 0x00300000, 0x00200080, 0x00407300,
- 0x00200084, 0x00800001, 0x00200510, 0x0060000a, 0x002037e0, 0x0040798a,
- 0x00201320, 0x00800029, 0x00407d84, 0x00201560, 0x00800002, 0x00409100,
- 0x00600006, 0x00700003, 0x00408ae6, 0x00700080, 0x0020007a, 0x0060000a,
- 0x00104280, 0x002002c8, 0x0060000a, 0x00200004, 0x00800001, 0x00700000,
- 0x00200000, 0x0060000a, 0x00106002, 0x0040ac84, 0x00700002, 0x00600004,
- 0x0040ac68, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x00700080,
- 0x00400a84, 0x00700002, 0x00400a68, 0x00500060, 0x00600007, 0x00409d88,
- 0x0060000f, 0x00000000, 0x00500060, 0x00200000, 0x0060000a, 0x00700000,
- 0x00106001, 0x00700083, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020,
- 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68, 0x0040ae06, 0x0040af05,
+ 0x00400889, 0x00200000, 0x0060000a, 0x00200000, 0x00300000, 0x00800001,
+ 0x00700009, 0x0060000e, 0x00400d64, 0x00400d05, 0x00409965, 0x00409e06,
+ 0x0040ac68, 0x00200000, 0x0060000a, 0x00700000, 0x00106000, 0x00700080,
+ 0x004014e6, 0x007000a0, 0x00401a84, 0x00700082, 0x00600001, 0x00500061,
+ 0x00600002, 0x00401b68, 0x00500060, 0x00200001, 0x0060000a, 0x0011814d,
+ 0x00110158, 0x00105401, 0x0020003a, 0x00100051, 0x001040c5, 0x0010c1c4,
+ 0x001041c9, 0x0010c1dc, 0x00150210, 0x0012c225, 0x00108238, 0x0010823e,
+ 0x001242c0, 0x00200040, 0x00100280, 0x00128100, 0x00128120, 0x00128143,
+ 0x0011415f, 0x0010815c, 0x0010c140, 0x00104029, 0x00110400, 0x00104d10,
+ 0x001046ec, 0x00500060, 0x00403a87, 0x0060000d, 0x00407de6, 0x002000f1,
+ 0x0060000a, 0x00148653, 0x00104668, 0x0010c66d, 0x00120682, 0x0011068b,
+ 0x00168691, 0x001046ae, 0x001046b0, 0x001206b4, 0x001046c4, 0x001146c6,
+ 0x001646cc, 0x001186e6, 0x001046ed, 0x001246f0, 0x002000c0, 0x00100700,
+ 0x0010c3d7, 0x001043e1, 0x00500060, 0x00405800, 0x00405884, 0x00600003,
+ 0x00500067, 0x00600008, 0x00500060, 0x00700082, 0x00200232, 0x0060000a,
+ 0x00104800, 0x00108901, 0x00104910, 0x00124920, 0x0020001f, 0x00100940,
+ 0x00140965, 0x00148a00, 0x00108a14, 0x00160b00, 0x00134b2c, 0x0010cd00,
+ 0x0010cd04, 0x0010cd08, 0x00104d80, 0x00104e00, 0x0012d600, 0x00105c00,
+ 0x00104f06, 0x002002c8, 0x0060000a, 0x00300000, 0x00200080, 0x00407300,
+ 0x00200084, 0x00800001, 0x00200510, 0x0060000a, 0x002037e0, 0x0040798a,
+ 0x00201320, 0x00800029, 0x00407d84, 0x00201560, 0x00800002, 0x00409100,
+ 0x00600006, 0x00700003, 0x00408ae6, 0x00700080, 0x0020007a, 0x0060000a,
+ 0x00104280, 0x002002c8, 0x0060000a, 0x00200004, 0x00800001, 0x00700000,
+ 0x00200000, 0x0060000a, 0x00106002, 0x0040ac84, 0x00700002, 0x00600004,
+ 0x0040ac68, 0x00700000, 0x00200000, 0x0060000a, 0x00106002, 0x00700080,
+ 0x00400a84, 0x00700002, 0x00400a68, 0x00500060, 0x00600007, 0x00409d88,
+ 0x0060000f, 0x00000000, 0x00500060, 0x00200000, 0x0060000a, 0x00700000,
+ 0x00106001, 0x00700083, 0x00910880, 0x00901ffe, 0x01940000, 0x00200020,
+ 0x0060000b, 0x00500069, 0x0060000c, 0x00401b68, 0x0040ae06, 0x0040af05,
0x00600009, 0x00700005, 0x00700006, 0x0060000e, ~0
};
NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, ctx_voodoo[i]);
i++;
}
- }
+ }
/* No context present currently */
NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
void nv40_graph_takedown(struct drm_device *dev)
{
}
-
nv40_mc_takedown(struct drm_device *dev)
{
}
-
DRM_ERROR("stub!\n");
return 0;
}
-
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
}
-int
+int
nv50_graph_init(struct drm_device *dev)
{
DRM_DEBUG("\n");
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst | (1<<31));
NV_WRITE(0x400824, NV_READ(0x400824) |
(save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
- NV40_PGRAPH_CTXCTL_0310_XFER_LOAD));
+ NV40_PGRAPH_CTXCTL_0310_XFER_LOAD));
NV_WRITE(NV40_PGRAPH_CTXCTL_0304, NV40_PGRAPH_CTXCTL_0304_XFER_CTX);
for (i = 0; i < tv; i++) {
return nv50_graph_transfer_context(dev, inst, 1);
}
-
return -ENOMEM;
dev_priv->Engine.instmem.priv = priv;
- /* Reserve the last MiB of VRAM, we should probably try to avoid
+ /* Reserve the last MiB of VRAM, we should probably try to avoid
* setting up the below tables over the top of the VBIOS image at
* some point.
*/
BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1);
else
BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009);
- BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
+ BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
}
BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
dev_priv->Engine.instmem.unbind(dev, gpuobj);
nouveau_mem_free(dev, gpuobj->im_backing);
gpuobj->im_backing = NULL;
- }
+ }
}
int
gpuobj->im_bound = 0;
return 0;
}
-
ring_start = dev_priv->cce_ring->offset - dev->agp->base;
else
#endif
- ring_start = dev_priv->cce_ring->offset -
+ ring_start = dev_priv->cce_ring->offset -
(unsigned long)dev->sg->virtual;
R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
write * sizeof(u32) ); \
} \
if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \
- DRM_ERROR( \
+ DRM_ERROR( \
"ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
((dev_priv->ring.tail + _nr) & tail_mask), \
write, __LINE__); \
if (cmd[0] & 0x8000) {
u32 offset;
- if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
+ if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
| RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
offset = cmd[2] << 10;
ret = !radeon_check_offset(dev_priv, offset);
DRM_ERROR("Invalid bitblt second offset is %08X\n", offset);
return -EINVAL;
}
-
+
}
}
u32 *ref_age_base;
u32 i, buf_idx, h_pending;
RING_LOCALS;
-
+
if (cmdbuf->bufsz < sizeof(uint64_t) + header.scratch.n_bufs * sizeof(buf_idx) ) {
return -EINVAL;
}
-
+
if (header.scratch.reg >= 5) {
return -EINVAL;
}
-
+
dev_priv->scratch_ages[header.scratch.reg] ++;
-
+
ref_age_base = (u32 *)(unsigned long)*((uint64_t *)cmdbuf->buf);
-
+
cmdbuf->buf += sizeof(uint64_t);
cmdbuf->bufsz -= sizeof(uint64_t);
-
+
for (i=0; i < header.scratch.n_bufs; i++) {
buf_idx = *(u32 *)cmdbuf->buf;
buf_idx *= 2; /* 8 bytes per buf */
-
+
if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) {
return -EINVAL;
}
-
+
if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) {
return -EINVAL;
}
-
+
if (h_pending == 0) {
return -EINVAL;
}
-
+
h_pending--;
-
+
if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) {
return -EINVAL;
}
-
+
cmdbuf->buf += sizeof(buf_idx);
cmdbuf->bufsz -= sizeof(buf_idx);
}
-
+
BEGIN_RING(2);
OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) );
OUT_RING( dev_priv->scratch_ages[header.scratch.reg] );
ADVANCE_RING();
-
+
return 0;
}
goto cleanup;
}
break;
-
+
default:
DRM_ERROR("bad cmd_type %i at %p\n",
header.header.cmd_type,
# define R300_TX_FORMAT_W8Z8Y8X8 0xC
# define R300_TX_FORMAT_W2Z10Y10X10 0xD
# define R300_TX_FORMAT_W16Z16Y16X16 0xE
-# define R300_TX_FORMAT_DXT1 0xF
-# define R300_TX_FORMAT_DXT3 0x10
-# define R300_TX_FORMAT_DXT5 0x11
+# define R300_TX_FORMAT_DXT1 0xF
+# define R300_TX_FORMAT_DXT3 0x10
+# define R300_TX_FORMAT_DXT5 0x11
# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */
-# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
-# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
-# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
+# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */
+# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */
+# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */
/* 0x16 - some 16 bit green format.. ?? */
# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */
# define R300_TX_FORMAT_CUBIC_MAP (1 << 26)
/* gap */
/* Floating point formats */
/* Note - hardware supports both 16 and 32 bit floating point */
-# define R300_TX_FORMAT_FL_I16 0x18
-# define R300_TX_FORMAT_FL_I16A16 0x19
+# define R300_TX_FORMAT_FL_I16 0x18
+# define R300_TX_FORMAT_FL_I16A16 0x19
# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A
-# define R300_TX_FORMAT_FL_I32 0x1B
-# define R300_TX_FORMAT_FL_I32A32 0x1C
+# define R300_TX_FORMAT_FL_I32 0x1B
+# define R300_TX_FORMAT_FL_I32A32 0x1C
# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D
/* alpha modes, convenience mostly */
/* if you have alpha, pick constant appropriate to the
number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */
-# define R300_TX_FORMAT_ALPHA_1CH 0x000
-# define R300_TX_FORMAT_ALPHA_2CH 0x200
-# define R300_TX_FORMAT_ALPHA_4CH 0x600
-# define R300_TX_FORMAT_ALPHA_NONE 0xA00
+# define R300_TX_FORMAT_ALPHA_1CH 0x000
+# define R300_TX_FORMAT_ALPHA_2CH 0x200
+# define R300_TX_FORMAT_ALPHA_4CH 0x600
+# define R300_TX_FORMAT_ALPHA_NONE 0xA00
/* Swizzling */
/* constants */
# define R300_TX_FORMAT_X 0
# define R300_RB3D_Z_DISABLED_2 0x00000014
# define R300_RB3D_Z_TEST 0x00000012
# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
-# define R300_RB3D_Z_WRITE_ONLY 0x00000006
+# define R300_RB3D_Z_WRITE_ONLY 0x00000006
# define R300_RB3D_Z_TEST 0x00000012
# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
-# define R300_RB3D_Z_WRITE_ONLY 0x00000006
+# define R300_RB3D_Z_WRITE_ONLY 0x00000006
# define R300_RB3D_STENCIL_ENABLE 0x00000001
#define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
{ 0x0000e571, 0x00000004 },
{ 0x0000e572, 0x0000000c },
{ 0x0000a000, 0x00000004 },
- { 0x0140a000, 0x00000004 },
+ { 0x0140a000, 0x00000004 },
{ 0x0000e568, 0x00000004 },
{ 0x000c2000, 0x00000004 },
{ 0x00000089, 0x00000018 },
{
u32 ring_start, cur_read_ptr;
u32 tmp;
-
+
/* Initialize the memory controller. With new memory map, the fb location
* is not changed, it should have been properly initialized already. Part
* of the problem is that the code below is bogus, assuming the GART is
return;
}
- tmp = RADEON_READ(RADEON_AIC_CNTL);
+ tmp = RADEON_READ(RADEON_AIC_CNTL);
if (on) {
RADEON_WRITE(RADEON_AIC_CNTL,
dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
& 0xffff) << 16;
- dev_priv->fb_size =
+ dev_priv->fb_size =
((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
- dev_priv->fb_location;
((base + dev_priv->gart_size) & 0xfffffffful) < base)
base = dev_priv->fb_location
- dev_priv->gart_size;
- }
+ }
dev_priv->gart_vm_start = base & 0xffc00000u;
if (dev_priv->gart_vm_start != base)
DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
#define R300_CMD_CP_DELAY 5
#define R300_CMD_DMA_DISCARD 6
#define R300_CMD_WAIT 7
-# define R300_WAIT_2D 0x1
-# define R300_WAIT_3D 0x2
-# define R300_WAIT_2D_CLEAN 0x3
-# define R300_WAIT_3D_CLEAN 0x4
+# define R300_WAIT_2D 0x1
+# define R300_WAIT_3D 0x2
+# define R300_WAIT_2D_CLEAN 0x3
+# define R300_WAIT_3D_CLEAN 0x4
#define R300_CMD_SCRATCH 8
typedef union {
unsigned int address;
} drm_radeon_surface_free_t;
-#define DRM_RADEON_VBLANK_CRTC1 1
-#define DRM_RADEON_VBLANK_CRTC2 2
+#define DRM_RADEON_VBLANK_CRTC1 1
+#define DRM_RADEON_VBLANK_CRTC2 2
#endif
#define RADEON_PCIE_INDEX 0x0030
#define RADEON_PCIE_DATA 0x0034
#define RADEON_PCIE_TX_GART_CNTL 0x10
-# define RADEON_PCIE_TX_GART_EN (1 << 0)
+# define RADEON_PCIE_TX_GART_EN (1 << 0)
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
-#define RADEON_PCIE_TX_GART_BASE 0x13
+#define RADEON_PCIE_TX_GART_BASE 0x13
#define RADEON_PCIE_TX_GART_START_LO 0x14
#define RADEON_PCIE_TX_GART_START_HI 0x15
#define RADEON_PCIE_TX_GART_END_LO 0x16
#define RADEON_GEN_INT_STATUS 0x0044
# define RADEON_CRTC_VBLANK_STAT (1 << 0)
-# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
+# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
-# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
+# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
# define RADEON_SW_INT_TEST (1 << 25)
-# define RADEON_SW_INT_TEST_ACK (1 << 25)
+# define RADEON_SW_INT_TEST_ACK (1 << 25)
# define RADEON_SW_INT_FIRE (1 << 26)
#define RADEON_HOST_PATH_CNTL 0x0130
*/
#define RADEON_RBBM_STATUS 0x0e40
/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
-/* #define RADEON_RBBM_STATUS 0x1740 */
+/* #define RADEON_RBBM_STATUS 0x1740 */
/* bits 6:0 are dword slots available in the cmd fifo */
# define RADEON_RBBM_FIFOCNT_MASK 0x007f
-# define RADEON_HIRQ_ON_RBB (1 << 8)
-# define RADEON_CPRQ_ON_RBB (1 << 9)
-# define RADEON_CFRQ_ON_RBB (1 << 10)
-# define RADEON_HIRQ_IN_RTBUF (1 << 11)
-# define RADEON_CPRQ_IN_RTBUF (1 << 12)
-# define RADEON_CFRQ_IN_RTBUF (1 << 13)
-# define RADEON_PIPE_BUSY (1 << 14)
-# define RADEON_ENG_EV_BUSY (1 << 15)
-# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
-# define RADEON_E2_BUSY (1 << 17)
-# define RADEON_RB2D_BUSY (1 << 18)
-# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
-# define RADEON_VAP_BUSY (1 << 20)
-# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
-# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
-# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
-# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
-# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
-# define RADEON_GA_BUSY (1 << 26)
-# define RADEON_CBA2D_BUSY (1 << 27)
-# define RADEON_RBBM_ACTIVE (1 << 31)
+# define RADEON_HIRQ_ON_RBB (1 << 8)
+# define RADEON_CPRQ_ON_RBB (1 << 9)
+# define RADEON_CFRQ_ON_RBB (1 << 10)
+# define RADEON_HIRQ_IN_RTBUF (1 << 11)
+# define RADEON_CPRQ_IN_RTBUF (1 << 12)
+# define RADEON_CFRQ_IN_RTBUF (1 << 13)
+# define RADEON_PIPE_BUSY (1 << 14)
+# define RADEON_ENG_EV_BUSY (1 << 15)
+# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
+# define RADEON_E2_BUSY (1 << 17)
+# define RADEON_RB2D_BUSY (1 << 18)
+# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
+# define RADEON_VAP_BUSY (1 << 20)
+# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
+# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
+# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
+# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
+# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
+# define RADEON_GA_BUSY (1 << 26)
+# define RADEON_CBA2D_BUSY (1 << 27)
+# define RADEON_RBBM_ACTIVE (1 << 31)
#define RADEON_RE_LINE_PATTERN 0x1cd0
#define RADEON_RE_MISC 0x26c4
#define RADEON_RE_TOP_LEFT 0x26c0
write, dev_priv->ring.tail ); \
} \
if (((dev_priv->ring.tail + _nr) & mask) != write) { \
- DRM_ERROR( \
+ DRM_ERROR( \
"ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
((dev_priv->ring.tail + _nr) & mask), \
write, __LINE__); \
return -EINVAL;
value = RADEON_SCRATCH_REG_OFFSET;
break;
-
+
case RADEON_PARAM_CARD_TYPE:
if (dev_priv->flags & RADEON_IS_PCIE)
value = RADEON_CARD_PCIE;
* MTRRs. */
dev_priv->mtrr[0].base = fb_base;
dev_priv->mtrr[0].size = 0x01000000;
- dev_priv->mtrr[0].handle =
+ dev_priv->mtrr[0].handle =
drm_mtrr_add(dev_priv->mtrr[0].base,
dev_priv->mtrr[0].size, DRM_MTRR_WC);
dev_priv->mtrr[1].base = fb_base+0x02000000;
dev_priv->mtrr[2].base = fb_base+0x04000000;
dev_priv->mtrr[2].size = 0x04000000;
dev_priv->mtrr[2].handle =
- drm_mtrr_add(dev_priv->mtrr[2].base,
+ drm_mtrr_add(dev_priv->mtrr[2].base,
dev_priv->mtrr[2].size, DRM_MTRR_WC);
} else {
DRM_ERROR("strange pci_resource_len %08lx\n",
* aperture. */
dev_priv->mtrr[0].base = fb_base;
dev_priv->mtrr[0].size = 0x08000000;
- dev_priv->mtrr[0].handle =
+ dev_priv->mtrr[0].handle =
drm_mtrr_add(dev_priv->mtrr[0].base,
dev_priv->mtrr[0].size, DRM_MTRR_WC);
} else {
}
front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8);
back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
- depth_stride =
+ depth_stride =
dev_priv->depth_pitch / (dev_priv->depth_bpp / 8);
dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE |
};
int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls);
-
*/
#define SAVAGE_STATUS_WORD0 0x48C00
#define SAVAGE_STATUS_WORD1 0x48C04
-#define SAVAGE_ALT_STATUS_WORD0 0x48C60
+#define SAVAGE_ALT_STATUS_WORD0 0x48C60
#define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff
#define SAVAGE_FIFO_USED_MASK_S4 0x001fffff
#define SAVAGE_DESTCTRL_S3D 0x34
#define SAVAGE_SCSTART_S3D 0x35
#define SAVAGE_SCEND_S3D 0x36
-#define SAVAGE_ZWATERMARK_S3D 0x37
+#define SAVAGE_ZWATERMARK_S3D 0x37
#define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38
/* common stuff */
#define SAVAGE_VERTBUFADDR 0x3e
uint32_t scstart = dev_priv->state.s3d.new_scstart;
uint32_t scend = dev_priv->state.s3d.new_scend;
scstart = (scstart & ~SAVAGE_SCISSOR_MASK_S3D) |
- ((uint32_t)pbox->x1 & 0x000007ff) |
+ ((uint32_t)pbox->x1 & 0x000007ff) |
(((uint32_t)pbox->y1 << 16) & 0x07ff0000);
scend = (scend & ~SAVAGE_SCISSOR_MASK_S3D) |
(((uint32_t)pbox->x2-1) & 0x000007ff) |
int ret = 0;
DRM_DEBUG("\n");
-
+
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (dma && dma->buflist) {
/* via_dma.c -- DMA support for the VIA Unichrome/Pro
- *
+ *
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
* All Rights Reserved.
- *
+ *
* Copyright 2004 The Unichrome project.
* All Rights Reserved.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
- * Authors:
- * Tungsten Graphics,
- * Erdi Chen,
+ * Authors:
+ * Tungsten Graphics,
+ * Erdi Chen,
* Thomas Hellstrom.
*/
dev_priv->dma_low +=8; \
}
-#define via_flush_write_combine() DRM_MEMORYBARRIER()
+#define via_flush_write_combine() DRM_MEMORYBARRIER()
#define VIA_OUT_RING_QW(w1,w2) \
*vb++ = (w1); \
*vb++ = (w2); \
- dev_priv->dma_low += 8;
+ dev_priv->dma_low += 8;
static void via_cmdbuf_start(drm_via_private_t * dev_priv);
static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
{
uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
-
- return ((hw_addr <= dev_priv->dma_low) ?
- (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
+
+ return ((hw_addr <= dev_priv->dma_low) ?
+ (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
(hw_addr - dev_priv->dma_low));
}
}
if (!dev->agp || !dev->agp->base) {
- DRM_ERROR("%s called with no agp memory available\n",
+ DRM_ERROR("%s called with no agp memory available\n",
__FUNCTION__);
return -EFAULT;
}
vb = via_get_dma(dev_priv);
VIA_OUT_RING_QW( HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
- (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
+ (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
- cmd_addr = (addr) ? addr :
+ cmd_addr = (addr) ? addr :
agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
(cmd_addr & HC_HAGPBpL_MASK));
command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
((end_addr & 0xff000000) >> 16));
- dev_priv->last_pause_ptr =
- via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
+ dev_priv->last_pause_ptr =
+ via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
&pause_addr_hi, & pause_addr_lo, 1) - 1;
via_flush_write_combine();
agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
&jump_addr_lo, 0);
-
+
dev_priv->dma_wrap = dev_priv->dma_low;
static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
{
- via_cmdbuf_jump(dev_priv);
+ via_cmdbuf_jump(dev_priv);
}
static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
}
#ifndef VIA_HAVE_DMABLIT
-int
+int
via_dma_blit_sync( struct drm_device *dev, void *data, struct drm_file *file_priv ) {
DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");
return -EINVAL;
}
-int
+int
via_dma_blit( struct drm_device *dev, void *data, struct drm_file *file_priv ) {
DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");
return -EINVAL;
#define VIA_DRM_DRIVER_PATCHLEVEL 1
#define VIA_DRM_DRIVER_VERSION (((VIA_DRM_DRIVER_MAJOR) << 16) | (VIA_DRM_DRIVER_MINOR))
-#define VIA_NR_SAREA_CLIPRECTS 8
+#define VIA_NR_SAREA_CLIPRECTS 8
#define VIA_NR_XVMC_PORTS 10
#define VIA_NR_XVMC_LOCKS 5
#define VIA_MAX_CACHELINE_SIZE 64
#define VIA_MEM_VIDEO 0 /* matches drm constant */
#define VIA_MEM_AGP 1 /* matches drm constant */
-#define VIA_MEM_SYSTEM 2
+#define VIA_MEM_SYSTEM 2
#define VIA_MEM_MIXED 3
#define VIA_MEM_UNKNOWN 4
unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
- unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
+ unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
/* Used by the 3d driver only at this point, for pageflipping:
*/
struct drm_wait_vblank_reply reply;
} drm_via_irqwait_t;
-typedef struct drm_via_blitsync {
+typedef struct drm_via_blitsync {
uint32_t sync_handle;
unsigned engine;
} drm_via_blitsync_t;
-/*
+/*
* Below,"flags" is currently unused but will be used for possible future
- * extensions like kernel space bounce buffers for bad alignments and
+ * extensions like kernel space bounce buffers for bad alignments and
* blit engine busy-wait polling for better latency in the absence of
* interrupts.
*/
unsigned char *mem_addr;
uint32_t mem_stride;
-
+
uint32_t flags;
int to_fb;
- drm_via_blitsync_t sync;
+ drm_via_blitsync_t sync;
} drm_via_dmablit_t;
uint32_t enable_mask;
wait_queue_head_t irq_queue;
} drm_via_irq_t;
-
+
typedef struct drm_via_private {
drm_via_sarea_t *sarea_priv;
drm_local_map_t *sarea;
drm_via_irq_t via_irqs[VIA_NUM_IRQS];
unsigned num_irqs;
maskarray_t *irq_masks;
- uint32_t irq_enable_mask;
- uint32_t irq_pending_mask;
+ uint32_t irq_enable_mask;
+ uint32_t irq_pending_mask;
int *irq_map;
/* Memory manager stuff */
#ifdef VIA_HAVE_CORE_MM
struct drm_mem_type_manager *man);
extern uint32_t via_evict_mask(struct drm_buffer_object *bo);
extern int via_move(struct drm_buffer_object *bo, int evict,
- int no_wait, struct drm_bo_mem_reg *new_mem);
+ int no_wait, struct drm_bo_mem_reg *new_mem);
#endif
#endif
/*
* Device-specific IRQs go here. This type might need to be extended with
* the register if there are multiple IRQ control registers.
- * Currently we activate the HQV interrupts of Unichrome Pro group A.
+ * Currently we activate the HQV interrupts of Unichrome Pro group A.
*/
static maskarray_t via_pro_group_a_irqs[] = {
0x00000000 },
{VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010,
0x00000000 },
- {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
+ {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
static int via_irqmap_pro_group_a[] = {0, 1, -1, 2, -1, 3};
static maskarray_t via_unichrome_irqs[] = {
- {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
+ {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008},
{VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
VIA_DMA_CSR_TA | VIA_DMA_CSR_TD, 0x00000008}
static int via_irqmap_unichrome[] = {-1, -1, -1, 0, -1, 1};
-static unsigned time_diff(struct timeval *now,struct timeval *then)
+static unsigned time_diff(struct timeval *now,struct timeval *then)
{
return (now->tv_usec >= then->tv_usec) ?
now->tv_usec - then->tv_usec :
microtime(&cur_vblank);
#endif
if (dev_priv->last_vblank_valid) {
- dev_priv->usec_per_vblank =
+ dev_priv->usec_per_vblank =
time_diff(&cur_vblank,
&dev_priv->last_vblank) >> 4;
}
drm_vbl_send_signals(dev);
handled = 1;
}
-
+
for (i=0; i<dev_priv->num_irqs; ++i) {
if (status & cur_irq->pending_mask) {
atomic_inc( &cur_irq->irq_received );
}
cur_irq++;
}
-
+
/* Acknowlege interrupts */
VIA_WRITE(VIA_REG_INTERRUPT, status);
if (dev_priv) {
/* Acknowlege interrupts */
status = VIA_READ(VIA_REG_INTERRUPT);
- VIA_WRITE(VIA_REG_INTERRUPT, status |
+ VIA_WRITE(VIA_REG_INTERRUPT, status |
dev_priv->irq_pending_mask);
}
}
DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
(((cur_vblank = atomic_read(&dev->vbl_received)) -
*sequence) <= (1 << 23)));
-
+
*sequence = cur_vblank;
return ret;
}
irq);
return -EINVAL;
}
-
+
real_irq = dev_priv->irq_map[irq];
if (real_irq < 0) {
if (masks[real_irq][2] && !force_sequence) {
DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
- ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
+ ((VIA_READ(masks[irq][2]) & masks[irq][3]) ==
masks[irq][4]));
cur_irq_sequence = atomic_read(&cur_irq->irq_received);
} else {
DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ,
(((cur_irq_sequence =
atomic_read(&cur_irq->irq_received)) -
- *sequence) <= (1 << 23)));
+ *sequence) <= (1 << 23)));
}
*sequence = cur_irq_sequence;
return ret;
for(i=0; i < dev_priv->num_irqs; ++i) {
atomic_set(&cur_irq->irq_received, 0);
- cur_irq->enable_mask = dev_priv->irq_masks[i][0];
+ cur_irq->enable_mask = dev_priv->irq_masks[i][0];
cur_irq->pending_mask = dev_priv->irq_masks[i][1];
DRM_INIT_WAITQUEUE( &cur_irq->irq_queue );
dev_priv->irq_enable_mask |= cur_irq->enable_mask;
dev_priv->irq_pending_mask |= cur_irq->pending_mask;
cur_irq++;
-
+
DRM_DEBUG("Initializing IRQ %d\n", i);
}
-
+
dev_priv->last_vblank_valid = 0;
/* Clear VSync interrupt regs */
status = VIA_READ(VIA_REG_INTERRUPT);
- VIA_WRITE(VIA_REG_INTERRUPT, status &
+ VIA_WRITE(VIA_REG_INTERRUPT, status &
~(dev_priv->irq_enable_mask));
-
+
/* Clear bits if they're already high */
viadrv_acknowledge_irqs(dev_priv);
}
VIA_WRITE8(0x83d4, 0x11);
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30);
-
+
}
}
VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30);
status = VIA_READ(VIA_REG_INTERRUPT);
- VIA_WRITE(VIA_REG_INTERRUPT, status &
+ VIA_WRITE(VIA_REG_INTERRUPT, status &
~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
}
}
return -EINVAL;
if (irqwait->request.irq >= dev_priv->num_irqs) {
- DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__,
+ DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__,
irqwait->request.irq);
return -EINVAL;
}
}
if (irqwait->request.type & VIA_IRQ_SIGNAL) {
- DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n",
+ DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n",
__FUNCTION__);
return -EINVAL;
}
/*
* Associates each hazard above with a possible multi-command
* sequence. For example an address that is split over multiple
- * commands and that needs to be checked at the first command
+ * commands and that needs to be checked at the first command
* that does not include any part of the address.
*/
}
/*
- * Require that all AGP texture levels reside in the same AGP map which should
+ * Require that all AGP texture levels reside in the same AGP map which should
* be mappable by the client. This is not a big restriction.
- * FIXME: To actually enforce this security policy strictly, drm_rmmap
- * would have to wait for dma quiescent before removing an AGP map.
+ * FIXME: To actually enforce this security policy strictly, drm_rmmap
+ * would have to wait for dma quiescent before removing an AGP map.
* The via_drm_lookup_agp_map call in reality seems to take
* very little CPU time.
*/
case check_texture_addr3:
cur_seq->unfinished = tex_address;
tmp = ((cmd >> 24) - HC_SubA_HTXnL0Pit);
- if (tmp == 0 &&
+ if (tmp == 0 &&
(cmd & HC_HTXnEnPit_MASK)) {
- cur_seq->pitch[cur_seq->texture][tmp] =
+ cur_seq->pitch[cur_seq->texture][tmp] =
(cmd & HC_HTXnLnPit_MASK);
cur_seq->tex_npot[cur_seq->texture] = 1;
} else {
cur_seq->pitch[cur_seq->texture][tmp] =
(cmd & HC_HTXnLnPitE_MASK) >> HC_HTXnLnPitE_SHIFT;
- cur_seq->tex_npot[cur_seq->texture] = 0;
+ cur_seq->tex_npot[cur_seq->texture] = 0;
if (cmd & 0x000FFFFF) {
DRM_ERROR
("Unimplemented texture level 0 pitch mode.\n");
state = via_check_vheader6(&buf, buf_end);
break;
case state_command:
- if ((HALCYON_HEADER2 == (cmd = *buf)) &&
+ if ((HALCYON_HEADER2 == (cmd = *buf)) &&
supported_3d)
state = state_header2;
else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
#define _VIA_VERIFIER_H_
typedef enum {
- no_sequence = 0,
+ no_sequence = 0,
z_address,
dest_address,
tex_address
typedef struct {
unsigned texture;
- uint32_t z_addr;
- uint32_t d_addr;
+ uint32_t z_addr;
+ uint32_t d_addr;
uint32_t t_addr[2][10];
uint32_t pitch[2][10];
uint32_t height[2][10];
- uint32_t tex_level_lo[2];
+ uint32_t tex_level_lo[2];
uint32_t tex_level_hi[2];
uint32_t tex_palette_size[2];
uint32_t tex_npot[2];
const uint32_t *buf_start;
} drm_via_state_t;
-extern int via_verify_command_stream(const uint32_t * buf, unsigned int size,
+extern int via_verify_command_stream(const uint32_t * buf, unsigned int size,
struct drm_device *dev, int agp);
extern int via_parse_command_stream(struct drm_device *dev, const uint32_t * buf,
unsigned int size);
struct xgi_mem_alloc {
/**
* Memory region to be used for allocation.
- *
+ *
* Must be one of XGI_MEMLOC_NON_LOCAL or XGI_MEMLOC_LOCAL.
*/
unsigned int location;
/**
* Number of bytes request.
- *
+ *
* On successful allocation, set to the actual number of bytes
* allocated.
*/
/**
* Magic handle used to release memory.
- *
+ *
* See also DRM_XGI_FREE ioctl.
*/
__u32 index;
projects / platform / upstream / libdrm.git / commitdiff