Value stored is never read.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
static int get_pmsts(PIIX4PMState *s)
{
int64_t d;
- int pmsts;
- pmsts = s->pmsts;
+
d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec());
if (d >= s->tmr_overflow_time)
s->pmsts |= TMROF_EN;
static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
{
// PIIX4PMState *s = opaque;
- addr &= 0x3f;
#ifdef DEBUG
+ addr &= 0x3f;
printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
#endif
}
irq2 = 7;
}
intno = s->pics[1].irq_base + irq2;
+#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
irq = irq2 + 8;
+#endif
} else {
intno = s->pics[0].irq_base + irq;
}
static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
{
- addr &= 7;
- pdebug("wecp%d=%02x\n", addr, val);
+ pdebug("wecp%d=%02x\n", addr & 7, val);
}
static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
{
uint8_t ret = 0xff;
- addr &= 7;
- pdebug("recp%d:%02x\n", addr, ret);
+
+ pdebug("recp%d:%02x\n", addr & 7, ret);
return ret;
}
ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
int bios_size, isa_bios_size;
PCIBus *pci_bus;
- ISADevice *isa_dev;
int piix3_devfn = -1;
- CPUState *env;
qemu_irq *cpu_irq;
qemu_irq *isa_irq;
qemu_irq *i8259;
}
for (i = 0; i < smp_cpus; i++) {
- env = pc_new_cpu(cpu_model);
+ pc_new_cpu(cpu_model);
}
vmport_init();
}
}
- isa_dev = isa_create_simple("i8042");
+ isa_create_simple("i8042");
DMA_init(0);
#ifdef HAS_AUDIO
audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
{
int dom, pci_bus;
unsigned slot;
- int type, bus;
+ int type;
PCIDevice *dev;
DriveInfo *dinfo = NULL;
const char *pci_addr = qdict_get_str(qdict, "pci_addr");
goto err;
}
type = dinfo->type;
- bus = drive_get_max_bus (type);
switch (type) {
case IF_SCSI:
int vretr_start_line;
int vretr_end_line;
- int div2, sldiv2, dots;
+ int dots;
+#if 0
+ int div2, sldiv2;
+#endif
int clocking_mode;
int clock_sel;
const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
vretr_end_line = s->cr[0x11] & 0xf;
- div2 = (s->cr[0x17] >> 2) & 1;
- sldiv2 = (s->cr[0x17] >> 3) & 1;
clocking_mode = (s->sr[0x01] >> 3) & 1;
clock_sel = (s->msr >> 2) & 3;
r->htotal = htotal_chars;
#if 0
+ div2 = (s->cr[0x17] >> 2) & 1;
+ sldiv2 = (s->cr[0x17] >> 3) & 1;
printf (
"hz=%f\n"
"htotal = %d\n"
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
gen_jmp_im(cur_eip);
- state_saved = 1;
}
svm_flags |= (1 << (4 + ot));
next_eip = s->pc - s->cs_base;
target_ulong pc_ptr;
uint16_t *gen_opc_end;
CPUBreakpoint *bp;
- int j, lj, cflags;
+ int j, lj;
uint64_t flags;
target_ulong pc_start;
target_ulong cs_base;
pc_start = tb->pc;
cs_base = tb->cs_base;
flags = tb->flags;
- cflags = tb->cflags;
dc->pe = (flags >> HF_PE_SHIFT) & 1;
dc->code32 = (flags >> HF_CS32_SHIFT) & 1;