}
return 1;
}
+ case X86ISD::FRCP:
+ return isNegatibleForFree(Op.getOperand(0), DAG, LegalOperations,
+ ForCodeSize, Depth + 1);
}
return TargetLowering::isNegatibleForFree(Op, DAG, LegalOperations,
NewOps[i] = Op.getOperand(i);
return DAG.getNode(NewOpc, SDLoc(Op), VT, NewOps);
}
+ case X86ISD::FRCP:
+ return DAG.getNode(Opc, SDLoc(Op), VT,
+ getNegatedExpression(Op.getOperand(0), DAG,
+ LegalOperations, ForCodeSize,
+ Depth + 1));
}
return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations,
define <4 x float> @test_fma_rcp_fneg_v4f32(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
; FMA3-LABEL: test_fma_rcp_fneg_v4f32:
; FMA3: # %bb.0: # %entry
-; FMA3-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2
; FMA3-NEXT: vrcpps %xmm2, %xmm2
-; FMA3-NEXT: vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
+; FMA3-NEXT: vfmsub213ps {{.*#+}} xmm0 = (xmm1 * xmm0) - xmm2
; FMA3-NEXT: retq
;
; FMA4-LABEL: test_fma_rcp_fneg_v4f32:
; FMA4: # %bb.0: # %entry
-; FMA4-NEXT: vxorps {{.*}}(%rip), %xmm2, %xmm2
; FMA4-NEXT: vrcpps %xmm2, %xmm2
-; FMA4-NEXT: vfmaddps %xmm2, %xmm1, %xmm0, %xmm0
+; FMA4-NEXT: vfmsubps %xmm2, %xmm1, %xmm0, %xmm0
; FMA4-NEXT: retq
entry:
%0 = fneg <4 x float> %z