net: dsa: mt7530: split-off common parts from mt7531_setup

MT7988 shares a significant part of the setup function with MT7531.
Split-off those parts into a shared function which is going to be used
also by mt7988_setup.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 9404675..47e3c41 100644 (file)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -2348,11 +2348,64 @@ mt7530_setup(struct dsa_switch *ds)
 }
 
 static int
+mt7531_setup_common(struct dsa_switch *ds)
+{
+       struct mt7530_priv *priv = ds->priv;
+       struct dsa_port *cpu_dp;
+       int ret, i;
+
+       /* BPDU to CPU port */
+       dsa_switch_for_each_cpu_port(cpu_dp, ds) {
+               mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
+                          BIT(cpu_dp->index));
+               break;
+       }
+       mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
+                  MT753X_BPDU_CPU_ONLY);
+
+       /* Enable and reset MIB counters */
+       mt7530_mib_reset(ds);
+
+       for (i = 0; i < MT7530_NUM_PORTS; i++) {
+               /* Disable forwarding by default on all ports */
+               mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+                          PCR_MATRIX_CLR);
+
+               /* Disable learning by default on all ports */
+               mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
+
+               mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
+
+               if (dsa_is_cpu_port(ds, i)) {
+                       ret = mt753x_cpu_port_enable(ds, i);
+                       if (ret)
+                               return ret;
+               } else {
+                       mt7530_port_disable(ds, i);
+
+                       /* Set default PVID to 0 on all user ports */
+                       mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
+                                  G0_PORT_VID_DEF);
+               }
+
+               /* Enable consistent egress tag */
+               mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
+                          PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
+       }
+
+       /* Flush the FDB table */
+       ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
+       if (ret < 0)
+               return ret;
+
+       return 0;
+}
+
+static int
 mt7531_setup(struct dsa_switch *ds)
 {
        struct mt7530_priv *priv = ds->priv;
        struct mt7530_dummy_poll p;
-       struct dsa_port *cpu_dp;
        u32 val, id;
        int ret, i;
 
@@ -2430,44 +2483,7 @@ mt7531_setup(struct dsa_switch *ds)
        mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
                                 CORE_PLL_GROUP4, val);
 
-       /* BPDU to CPU port */
-       dsa_switch_for_each_cpu_port(cpu_dp, ds) {
-               mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
-                          BIT(cpu_dp->index));
-               break;
-       }
-       mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
-                  MT753X_BPDU_CPU_ONLY);
-
-       /* Enable and reset MIB counters */
-       mt7530_mib_reset(ds);
-
-       for (i = 0; i < MT7530_NUM_PORTS; i++) {
-               /* Disable forwarding by default on all ports */
-               mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
-                          PCR_MATRIX_CLR);
-
-               /* Disable learning by default on all ports */
-               mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
-
-               mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
-
-               if (dsa_is_cpu_port(ds, i)) {
-                       ret = mt753x_cpu_port_enable(ds, i);
-                       if (ret)
-                               return ret;
-               } else {
-                       mt7530_port_disable(ds, i);
-
-                       /* Set default PVID to 0 on all user ports */
-                       mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
-                                  G0_PORT_VID_DEF);
-               }
-
-               /* Enable consistent egress tag */
-               mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
-                          PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
-       }
+       mt7531_setup_common(ds);
 
        /* Setup VLAN ID 0 for VLAN-unaware bridges */
        ret = mt7530_setup_vlan0(priv);
@@ -2477,11 +2493,6 @@ mt7531_setup(struct dsa_switch *ds)
        ds->assisted_learning_on_cpu_port = true;
        ds->mtu_enforcement_ingress = true;
 
-       /* Flush the FDB table */
-       ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
-       if (ret < 0)
-               return ret;
-
        return 0;
 }