struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint32_t enabled_stream_buffers_mask = 0;
+ ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
+
if (cmd_buffer->state.last_vgt_shader) {
enabled_stream_buffers_mask = cmd_buffer->state.last_vgt_shader->info.so.enabled_stream_buffers_mask;
}
radeon_emit(cs, so->hw_enabled_mask & enabled_stream_buffers_mask);
cmd_buffer->state.context_roll_without_scissor_emitted = true;
+
+ assert(cs->cdw <= cdw_max);
}
static void
struct radeon_cmdbuf *cs = cmd_buffer->cs;
unsigned reg_strmout_cntl;
+ ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 14);
+
/* The register is at different places on different ASICs. */
if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
radeon_emit(cs, 4); /* poll interval */
+
+ assert(cs->cdw <= cdw_max);
}
VKAPI_ATTR void VKAPI_CALL
radv_flush_vgt_streamout(cmd_buffer);
}
+ ASSERTED unsigned cdw_max =
+ radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, MAX_SO_BUFFERS * 10);
+
u_foreach_bit(i, so->enabled_mask)
{
int32_t counter_buffer_idx = i - firstCounterBuffer;
}
}
+ assert(cs->cdw <= cdw_max);
+
radv_set_streamout_enable(cmd_buffer, true);
}
if (!cmd_buffer->device->physical_device->use_ngg_streamout)
radv_flush_vgt_streamout(cmd_buffer);
+ ASSERTED unsigned cdw_max =
+ radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, MAX_SO_BUFFERS * 12);
+
u_foreach_bit(i, so->enabled_mask)
{
int32_t counter_buffer_idx = i - firstCounterBuffer;
}
}
+ assert(cmd_buffer->cs->cdw <= cdw_max);
+
radv_set_streamout_enable(cmd_buffer, false);
}