[AArch64] Tweak gcc.target/aarch64/sve/clastb_8.c

clastb_8.c was using scan-tree-dump-times to check for fully-masked
loops, which made it sensitive to the number of times we try to
vectorize.

2019-11-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/testsuite/
	* gcc.target/aarch64/sve/clastb_8.c: Use assembly tests to
	check for fully-masked loops.

From-SVN: r278340

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4274edd..8b48698 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,10 @@
 2019-11-16  Richard Sandiford  <richard.sandiford@arm.com>
 
+       * gcc.target/aarch64/sve/clastb_8.c: Use assembly tests to
+       check for fully-masked loops.
+
+2019-11-16  Richard Sandiford  <richard.sandiford@arm.com>
+
        * gcc.target/aarch64/sve/reduc_3.c: Split multi-vector cases out
        into...
        * gcc.target/aarch64/sve/reduc_3_costly.c: ...this new test,

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/clastb_8.c b/gcc/testsuite/gcc.target/aarch64/sve/clastb_8.c
index 583fc8d..57c4208 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/clastb_8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/clastb_8.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target aarch64_asm_sve_ok } } */
-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details -msve-vector-bits=256 --save-temps" } */
+/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=256 --save-temps" } */
 
 #include <stdint.h>
 
@@ -19,8 +19,11 @@ TEST_TYPE (uint16_t);
 TEST_TYPE (uint32_t);
 TEST_TYPE (uint64_t);
 
-/* { dg-final { scan-tree-dump-times "using a fully-masked loop." 4 "vect" } } */
 /* { dg-final { scan-assembler {\tclastb\t(b[0-9]+), p[0-7], \1, z[0-9]+\.b\n} } } */
 /* { dg-final { scan-assembler {\tclastb\t(h[0-9]+), p[0-7], \1, z[0-9]+\.h\n} } } */
 /* { dg-final { scan-assembler {\tclastb\t(s[0-9]+), p[0-7], \1, z[0-9]+\.s\n} } } */
 /* { dg-final { scan-assembler {\tclastb\t(d[0-9]+), p[0-7], \1, z[0-9]+\.d\n} } } */
+/* { dg-final { scan-assembler {\twhilelo\tp[0-9]+\.b,} } } */
+/* { dg-final { scan-assembler {\twhilelo\tp[0-9]+\.h,} } } */
+/* { dg-final { scan-assembler {\twhilelo\tp[0-9]+\.s,} } } */
+/* { dg-final { scan-assembler {\twhilelo\tp[0-9]+\.d,} } } */