#include <asm/pl310.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
+#include <sdhci.h>
#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
}
#endif
+#ifdef CONFIG_MV_SDHCI
+int board_mmc_init(bd_t *bis)
+{
+ mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
+ SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
+
+ return 0;
+}
+#endif
+
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
int mvebu_mbus_probe(struct mbus_win windows[], int count);
int mvebu_soc_family(void);
+int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
+
/*
* Highspeed SERDES PHY config init, ported from bin_hdr
* to mainline U-Boot
--- /dev/null
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MACH_MVEBU_GPIO_H
+#define __MACH_MVEBU_GPIO_H
+
+/* Empty file - sdhci requires this. */
+
+#endif
#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
+#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
#define SDRAM_MAX_CS 4
#define SDRAM_ADDR_MASK 0xFF000000