[X86] Merge VMOVMSKBrr and MOVMSKBrr in the SNB sheduler model.
authorCraig Topper <craig.topper@intel.com>
Fri, 23 Mar 2018 06:41:38 +0000 (06:41 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 23 Mar 2018 06:41:38 +0000 (06:41 +0000)
The VMOVMSKBrr was in a separate InstRW with a lower latency, but I assume they should be the same and the higher latency matches Agners table so I'm going with that.

llvm-svn: 328291

llvm/lib/Target/X86/X86SchedSandyBridge.td
llvm/test/CodeGen/X86/sse2-schedule.ll

index 155aa743d69e9d4330bbbf0a3270c2cd6e5a2573..89d3a5f537bdcb82959876a4e7e9cbbb2ca5457b 100644 (file)
@@ -258,8 +258,7 @@ def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SBWriteResGroup0], (instregex "VPMOVMSKBrr",
-                                           "(V?)CVTSS2SDrr",
+def: InstRW<[SBWriteResGroup0], (instregex "(V?)CVTSS2SDrr",
                                            "(V?)PSLLDri",
                                            "(V?)PSLLQri",
                                            "(V?)PSLLWri",
@@ -551,7 +550,7 @@ def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> {
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SBWriteResGroup7], (instregex "PMOVMSKBrr",
+def: InstRW<[SBWriteResGroup7], (instregex "(V?)PMOVMSKBrr",
                                            "VMOVMSKPDYrr",
                                            "(V?)MOVMSKPDrr",
                                            "VMOVMSKPSYrr",
index 37edfa0f2d9d5daa4a606c62245913dfa2859fd6..f9d7c995e7569964031483abd4f2a0f903c7555c 100644 (file)
@@ -5987,7 +5987,7 @@ define i32 @test_pmovmskb(<16 x i8> %a0) {
 ;
 ; SANDY-LABEL: test_pmovmskb:
 ; SANDY:       # %bb.0:
-; SANDY-NEXT:    vpmovmskb %xmm0, %eax # sched: [1:1.00]
+; SANDY-NEXT:    vpmovmskb %xmm0, %eax # sched: [2:1.00]
 ; SANDY-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-LABEL: test_pmovmskb: