pinctrl: renesas: rzg2l: Add support to get/set pin config for GPIO port pins

Add support to get/set pin config for GPIO port pins.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211110224622.16022-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 4465402..a5c4bfb 100644 (file)
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -106,6 +106,7 @@
 #define PM_OUTPUT              0x2
 
 #define RZG2L_PIN_ID_TO_PORT(id)       ((id) / RZG2L_PINS_PER_PORT)
+#define RZG2L_PIN_ID_TO_PORT_OFFSET(id)        (RZG2L_PIN_ID_TO_PORT(id) + 0x10)
 #define RZG2L_PIN_ID_TO_PIN(id)                ((id) % RZG2L_PINS_PER_PORT)
 
 struct rzg2l_dedicated_configs {
@@ -424,6 +425,23 @@ done:
        return ret;
 }
 
+static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
+                                  u32 cfg, u32 port, u8 bit)
+{
+       u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);
+       u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg);
+       u32 data;
+
+       if (bit >= pincount || port >= pctrl->data->n_port_pins)
+               return -EINVAL;
+
+       data = pctrl->data->port_pin_configs[port];
+       if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data))
+               return -EINVAL;
+
+       return 0;
+}
+
 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
                                 u8 bit, u32 mask)
 {
@@ -466,9 +484,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
        const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
        unsigned int *pin_data = pin->drv_data;
        unsigned int arg = 0;
-       u32 port_offset = 0;
        unsigned long flags;
        void __iomem *addr;
+       u32 port_offset;
        u32 cfg = 0;
        u8 bit = 0;
 
@@ -479,6 +497,13 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
                port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);
                cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
                bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
+       } else {
+               cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
+               port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
+               bit = RZG2L_PIN_ID_TO_PIN(_pin);
+
+               if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
+                       return -EINVAL;
        }
 
        switch (param) {
@@ -525,9 +550,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
        const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
        unsigned int *pin_data = pin->drv_data;
        enum pin_config_param param;
-       u32 port_offset = 0;
        unsigned long flags;
        void __iomem *addr;
+       u32 port_offset;
        unsigned int i;
        u32 cfg = 0;
        u8 bit = 0;
@@ -539,6 +564,13 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
                port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data);
                cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
                bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
+       } else {
+               cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
+               port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
+               bit = RZG2L_PIN_ID_TO_PIN(_pin);
+
+               if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
+                       return -EINVAL;
        }
 
        for (i = 0; i < num_configs; i++) {