ppc/p4080: Handle timebase enabling and frequency reporting

On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
the core not longer controls the enabling of the timebase.  We now need
to enable the boot core's timebase via CCSR register writes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index bdd9ee4c83348ec8ba018373d7c529bddb36e667..25c04169fd940aa6f31e8c3584f0a1ff5b8bd746 100644 (file)
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
  */
 unsigned long get_tbclk (void)
 {
+#ifdef CONFIG_FSL_CORENET
+       return (gd->bus_clk + 8) / 16;
+#else
        return (gd->bus_clk + 4UL)/8UL;
+#endif
 }
 
 

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a8d83b1c8a3d73f4c000beee5a8ca2ff981a6a45..53369349d13a3d19fd2adc83ee58c4941b69e77a 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -136,6 +136,20 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
  * initialize a bunch of registers
  */
 
+#ifdef CONFIG_FSL_CORENET
+static void corenet_tb_init(void)
+{
+       volatile ccsr_rcpm_t *rcpm =
+               (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+       volatile ccsr_pic_t *pic =
+               (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+       u32 whoami = in_be32(&pic->whoami);
+
+       /* Enable the timebase register for this core */
+       out_be32(&rcpm->ctbenrl, (1 << whoami));
+}
+#endif
+
 void cpu_init_f (void)
 {
        volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
@@ -229,6 +243,9 @@ void cpu_init_f (void)
 #if defined(CONFIG_FSL_DMA)
        dma_init();
 #endif
+#ifdef CONFIG_FSL_CORENET
+       corenet_tb_init();
+#endif
 }
 
 

diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 61e0fb0636dc78b14374217a8c852933c0e852d3..efb651882260266dafcd1328a9c80272e178c6f3 100644 (file)
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -294,7 +294,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
        fdt_add_enet_stashing(blob);
 
        do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-               "timebase-frequency", bd->bi_busfreq / 8, 1);
+               "timebase-frequency", get_tbclk(), 1);
        do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
                "bus-frequency", bd->bi_busfreq, 1);
        get_sys_info(&sysinfo);