[X86][SSE] Updated test so that both are applying the post-multiply

This is to ensure that there are no diffs other than due to buildvector/legalization

llvm-svn: 276882

diff --git a/llvm/test/CodeGen/X86/cvtv2f32.ll b/llvm/test/CodeGen/X86/cvtv2f32.ll
index 38e03ed..da46d36 100644 (file)
--- a/llvm/test/CodeGen/X86/cvtv2f32.ll
+++ b/llvm/test/CodeGen/X86/cvtv2f32.ll
@@ -38,27 +38,30 @@ define <2 x float> @uitofp_2i32_buildvector(i32 %x, i32 %y, <2 x float> %v) {
   ret <2 x float> %t5
 }
 
-define <2 x float> @uitofp_2i32_legalized(<2 x i32> %in) {
+define <2 x float> @uitofp_2i32_legalized(<2 x i32> %in, <2 x float> %v) {
 ; X32-LABEL: uitofp_2i32_legalized:
 ; X32:       # BB#0:
-; X32-NEXT:    pxor %xmm1, %xmm1
-; X32-NEXT:    pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; X32-NEXT:    pxor %xmm2, %xmm2
+; X32-NEXT:    pblendw {{.*#+}} xmm2 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
 ; X32-NEXT:    movdqa {{.*#+}} xmm0 = [4.503600e+15,4.503600e+15]
-; X32-NEXT:    por %xmm0, %xmm1
-; X32-NEXT:    subpd %xmm0, %xmm1
-; X32-NEXT:    cvtpd2ps %xmm1, %xmm0
+; X32-NEXT:    por %xmm0, %xmm2
+; X32-NEXT:    subpd %xmm0, %xmm2
+; X32-NEXT:    cvtpd2ps %xmm2, %xmm0
+; X32-NEXT:    mulps %xmm1, %xmm0
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: uitofp_2i32_legalized:
 ; X64:       # BB#0:
 ; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
-; X64-NEXT:    movdqa {{.*#+}} xmm1 = [1258291200,1258291200,1258291200,1258291200]
-; X64-NEXT:    pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+; X64-NEXT:    movdqa {{.*#+}} xmm2 = [1258291200,1258291200,1258291200,1258291200]
+; X64-NEXT:    pblendw {{.*#+}} xmm2 = xmm0[0],xmm2[1],xmm0[2],xmm2[3],xmm0[4],xmm2[5],xmm0[6],xmm2[7]
 ; X64-NEXT:    psrld $16, %xmm0
 ; X64-NEXT:    pblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
 ; X64-NEXT:    addps {{.*}}(%rip), %xmm0
-; X64-NEXT:    addps %xmm1, %xmm0
+; X64-NEXT:    addps %xmm2, %xmm0
+; X64-NEXT:    mulps %xmm1, %xmm0
 ; X64-NEXT:    retq
-  %r = uitofp <2 x i32> %in to <2 x float>
-  ret <2 x float> %r
+  %t1 = uitofp <2 x i32> %in to <2 x float>
+  %t2 = fmul <2 x float> %v, %t1
+  ret <2 x float> %t2
 }