[AArch64] Add coverage for select(icmp(x,y),sub(x,y),sub(y,x)) -> abd(x,y) patterns

diff --git a/llvm/test/CodeGen/AArch64/abd-combine.ll b/llvm/test/CodeGen/AArch64/abd-combine.ll
index a5be2cd..e7fbbfe 100644 (file)
--- a/llvm/test/CodeGen/AArch64/abd-combine.ll
+++ b/llvm/test/CodeGen/AArch64/abd-combine.ll
@@ -104,6 +104,125 @@ define <8 x i16> @abdu_undef(<8 x i16> %src1) {
   ret <8 x i16> %result
 }
 
+define <8 x i16> @abdu_ugt(<8 x i16>, <8 x i16>) {
+; CHECK-LABEL: abdu_ugt:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmhi v2.8h, v0.8h, v1.8h
+; CHECK-NEXT:    sub v3.8h, v0.8h, v1.8h
+; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    bit v0.16b, v3.16b, v2.16b
+; CHECK-NEXT:    ret
+  %3 = icmp ugt <8 x i16> %0, %1
+  %4 = sub <8 x i16> %0, %1
+  %5 = sub <8 x i16> %1, %0
+  %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
+  ret <8 x i16> %6
+}
+
+define <8 x i16> @abdu_uge(<8 x i16>, <8 x i16>) {
+; CHECK-LABEL: abdu_uge:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmhs v2.8h, v0.8h, v1.8h
+; CHECK-NEXT:    sub v3.8h, v0.8h, v1.8h
+; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    bit v0.16b, v3.16b, v2.16b
+; CHECK-NEXT:    ret
+  %3 = icmp uge <8 x i16> %0, %1
+  %4 = sub <8 x i16> %0, %1
+  %5 = sub <8 x i16> %1, %0
+  %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
+  ret <8 x i16> %6
+}
+
+define <8 x i16> @abdu_ult(<8 x i16>, <8 x i16>) {
+; CHECK-LABEL: abdu_ult:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmhi v2.8h, v1.8h, v0.8h
+; CHECK-NEXT:    sub v3.8h, v0.8h, v1.8h
+; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    bif v0.16b, v3.16b, v2.16b
+; CHECK-NEXT:    ret
+  %3 = icmp ult <8 x i16> %0, %1
+  %4 = sub <8 x i16> %0, %1
+  %5 = sub <8 x i16> %1, %0
+  %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
+  ret <8 x i16> %6
+}
+
+define <8 x i16> @abdu_ule(<8 x i16>, <8 x i16>) {
+; CHECK-LABEL: abdu_ule:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmhs v2.8h, v1.8h, v0.8h
+; CHECK-NEXT:    sub v3.8h, v0.8h, v1.8h
+; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    bif v0.16b, v3.16b, v2.16b
+; CHECK-NEXT:    ret
+  %3 = icmp ule <8 x i16> %0, %1
+  %4 = sub <8 x i16> %0, %1
+  %5 = sub <8 x i16> %1, %0
+  %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
+  ret <8 x i16> %6
+}
+
+define <8 x i16> @abds_sgt(<8 x i16>, <8 x i16>) {
+; CHECK-LABEL: abds_sgt:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmgt v2.8h, v0.8h, v1.8h
+; CHECK-NEXT:    sub v3.8h, v0.8h, v1.8h
+; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    bit v0.16b, v3.16b, v2.16b
+; CHECK-NEXT:    ret
+  %3 = icmp sgt <8 x i16> %0, %1
+  %4 = sub <8 x i16> %0, %1
+  %5 = sub <8 x i16> %1, %0
+  %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
+  ret <8 x i16> %6
+}
+
+define <8 x i16> @abds_sge(<8 x i16>, <8 x i16>) {
+; CHECK-LABEL: abds_sge:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmge v2.8h, v0.8h, v1.8h
+; CHECK-NEXT:    sub v3.8h, v0.8h, v1.8h
+; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    bit v0.16b, v3.16b, v2.16b
+; CHECK-NEXT:    ret
+  %3 = icmp sge <8 x i16> %0, %1
+  %4 = sub <8 x i16> %0, %1
+  %5 = sub <8 x i16> %1, %0
+  %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
+  ret <8 x i16> %6
+}
+
+define <8 x i16> @abds_slt(<8 x i16>, <8 x i16>) {
+; CHECK-LABEL: abds_slt:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmgt v2.8h, v1.8h, v0.8h
+; CHECK-NEXT:    sub v3.8h, v0.8h, v1.8h
+; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    bif v0.16b, v3.16b, v2.16b
+; CHECK-NEXT:    ret
+  %3 = icmp slt <8 x i16> %0, %1
+  %4 = sub <8 x i16> %0, %1
+  %5 = sub <8 x i16> %1, %0
+  %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
+  ret <8 x i16> %6
+}
+
+define <8 x i16> @abds_sle(<8 x i16>, <8 x i16>) {
+; CHECK-LABEL: abds_sle:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmge v2.8h, v1.8h, v0.8h
+; CHECK-NEXT:    sub v3.8h, v0.8h, v1.8h
+; CHECK-NEXT:    sub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    bif v0.16b, v3.16b, v2.16b
+; CHECK-NEXT:    ret
+  %3 = icmp sle <8 x i16> %0, %1
+  %4 = sub <8 x i16> %0, %1
+  %5 = sub <8 x i16> %1, %0
+  %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
+  ret <8 x i16> %6
+}
 
 
 define <8 x i16> @abdu_i_base(<8 x i16> %src1, <8 x i16> %src2) {