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[llvm-mca] Add new tests for Exynos (NFC)
authorEvandro Menezes <e.menezes@samsung.com>
Mon, 10 Dec 2018 16:22:29 +0000 (16:22 +0000)
committerEvandro Menezes <e.menezes@samsung.com>
Mon, 10 Dec 2018 16:22:29 +0000 (16:22 +0000)
llvm-svn: 348766

llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s [new file with mode: 0644] patch | blob
llvm/test/tools/llvm-mca/AArch64/Exynos/register-offset.s [new file with mode: 0644] patch | blob
llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s [new file with mode: 0644] patch | blob

diff --git a/llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s b/llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s
new file mode 100644 (file)
index 0000000..58fb4f0
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Exynos/extended-register.s
@@ -0,0 +1,58 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m1  -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM1
+# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3  -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM3
+
+  sub  w0, w1, w2, sxtb #0
+  add  w3, w4, w5, sxth #1
+  subs x6, x7, w8, uxtw #2
+  adds x9, x10, x11, uxtx #3
+  sub  w12, w13, w14, uxtb #3
+  add  w15, w16, w17, uxth #2
+  subs x18, x19, w20, sxtw #1
+  adds x21, x22, x23, sxtx #0
+
+# ALL:      Iterations:        100
+# ALL-NEXT: Instructions:      800
+
+# EM1-NEXT: Total Cycles:      537
+# EM3-NEXT: Total Cycles:      403
+
+# ALL-NEXT: Total uOps:        800
+
+# EM1:      Dispatch Width:    4
+# EM1-NEXT: uOps Per Cycle:    1.49
+# EM1-NEXT: IPC:               1.49
+# EM1-NEXT: Block RThroughput: 5.3
+
+# EM3:      Dispatch Width:    6
+# EM3-NEXT: uOps Per Cycle:    1.99
+# EM3-NEXT: IPC:               1.99
+# EM3-NEXT: Block RThroughput: 4.0
+
+# ALL:      Instruction Info:
+# ALL-NEXT: [1]: #uOps
+# ALL-NEXT: [2]: Latency
+# ALL-NEXT: [3]: RThroughput
+# ALL-NEXT: [4]: MayLoad
+# ALL-NEXT: [5]: MayStore
+# ALL-NEXT: [6]: HasSideEffects (U)
+
+# ALL:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+
+# EM1-NEXT:  1      2     0.67                        sub      w0, w1, w2, sxtb
+# EM1-NEXT:  1      2     0.67                        add      w3, w4, w5, sxth #1
+# EM1-NEXT:  1      2     0.67                        subs     x6, x7, w8, uxtw #2
+# EM1-NEXT:  1      2     0.67                        adds     x9, x10, x11, uxtx #3
+# EM1-NEXT:  1      2     0.67                        sub      w12, w13, w14, uxtb #3
+# EM1-NEXT:  1      2     0.67                        add      w15, w16, w17, uxth #2
+# EM1-NEXT:  1      2     0.67                        subs     x18, x19, w20, sxtw #1
+# EM1-NEXT:  1      2     0.67                        adds     x21, x22, x23, sxtx
+
+# EM3-NEXT:  1      2     0.50                        sub      w0, w1, w2, sxtb
+# EM3-NEXT:  1      2     0.50                        add      w3, w4, w5, sxth #1
+# EM3-NEXT:  1      2     0.50                        subs     x6, x7, w8, uxtw #2
+# EM3-NEXT:  1      2     0.50                        adds     x9, x10, x11, uxtx #3
+# EM3-NEXT:  1      2     0.50                        sub      w12, w13, w14, uxtb #3
+# EM3-NEXT:  1      2     0.50                        add      w15, w16, w17, uxth #2
+# EM3-NEXT:  1      2     0.50                        subs     x18, x19, w20, sxtw #1
+# EM3-NEXT:  1      2     0.50                        adds     x21, x22, x23, sxtx
diff --git a/llvm/test/tools/llvm-mca/AArch64/Exynos/register-offset.s b/llvm/test/tools/llvm-mca/AArch64/Exynos/register-offset.s
new file mode 100644 (file)
index 0000000..fe1c75e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Exynos/register-offset.s
@@ -0,0 +1,46 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m1  -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM1
+# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3  -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM3
+
+  ldr  w0, [x1, x2, lsl #0]
+  str  x3, [x4, w5, sxtw #0]
+  ldr  x6, [x7, w8, uxtw #3]
+  str  x9, [x10, x11, lsl #3]
+
+# ALL:      Iterations:        100
+# ALL-NEXT: Instructions:      400
+
+# EM1-NEXT: Total Cycles:      408
+# EM3-NEXT: Total Cycles:      208
+
+# ALL-NEXT: Total uOps:        800
+
+# EM1:      Dispatch Width:    4
+# EM1-NEXT: uOps Per Cycle:    1.96
+# EM1-NEXT: IPC:               0.98
+# EM1-NEXT: Block RThroughput: 2.0
+
+# EM3:      Dispatch Width:    6
+# EM3-NEXT: uOps Per Cycle:    3.85
+# EM3-NEXT: IPC:               1.92
+# EM3-NEXT: Block RThroughput: 2.0
+
+# ALL:      Instruction Info:
+# ALL-NEXT: [1]: #uOps
+# ALL-NEXT: [2]: Latency
+# ALL-NEXT: [3]: RThroughput
+# ALL-NEXT: [4]: MayLoad
+# ALL-NEXT: [5]: MayStore
+# ALL-NEXT: [6]: HasSideEffects (U)
+
+# ALL:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+
+# EM1-NEXT:  2      5     1.00    *                   ldr      w0, [x1, x2]
+# EM1-NEXT:  2      2     1.00           *            str      x3, [x4, w5, sxtw]
+# EM1-NEXT:  2      5     1.00    *                   ldr      x6, [x7, w8, uxtw #3]
+# EM1-NEXT:  2      2     1.00           *            str      x9, [x10, x11, lsl #3]
+
+# EM3-NEXT:  2      5     0.50    *                   ldr      w0, [x1, x2]
+# EM3-NEXT:  2      1     1.00           *            str      x3, [x4, w5, sxtw]
+# EM3-NEXT:  2      5     0.50    *                   ldr      x6, [x7, w8, uxtw #3]
+# EM3-NEXT:  2      1     1.00           *            str      x9, [x10, x11, lsl #3]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s b/llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s
new file mode 100644 (file)
index 0000000..4b73836
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/AArch64/Exynos/shifted-register.s
@@ -0,0 +1,46 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m1  -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM1
+# RUN: llvm-mca -march=aarch64 -mcpu=exynos-m3  -resource-pressure=false < %s | FileCheck %s -check-prefixes=ALL,EM3
+
+  add  w0, w1, w2, lsl #0
+  sub  x3, x4, x5, lsr #1
+  adds x6, x7, x8, lsl #2
+  subs w9, w10, w11, asr #3
+
+# ALL:      Iterations:        100
+# ALL-NEXT: Instructions:      400
+
+# EM1-NEXT: Total Cycles:      271
+# EM3-NEXT: Total Cycles:      203
+
+# ALL-NEXT: Total uOps:        400
+
+# EM1:      Dispatch Width:    4
+# EM1-NEXT: uOps Per Cycle:    1.48
+# EM1-NEXT: IPC:               1.48
+# EM1-NEXT: Block RThroughput: 2.7
+
+# EM3:      Dispatch Width:    6
+# EM3-NEXT: uOps Per Cycle:    1.97
+# EM3-NEXT: IPC:               1.97
+# EM3-NEXT: Block RThroughput: 2.0
+
+# ALL:      Instruction Info:
+# ALL-NEXT: [1]: #uOps
+# ALL-NEXT: [2]: Latency
+# ALL-NEXT: [3]: RThroughput
+# ALL-NEXT: [4]: MayLoad
+# ALL-NEXT: [5]: MayStore
+# ALL-NEXT: [6]: HasSideEffects (U)
+
+# ALL:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+
+# EM1-NEXT:  1      2     0.67                        add      w0, w1, w2
+# EM1-NEXT:  1      2     0.67                        sub      x3, x4, x5, lsr #1
+# EM1-NEXT:  1      2     0.67                        adds     x6, x7, x8, lsl #2
+# EM1-NEXT:  1      2     0.67                        subs     w9, w10, w11, asr #3
+
+# EM3-NEXT:  1      2     0.50                        add      w0, w1, w2
+# EM3-NEXT:  1      2     0.50                        sub      x3, x4, x5, lsr #1
+# EM3-NEXT:  1      2     0.50                        adds     x6, x7, x8, lsl #2
+# EM3-NEXT:  1      2     0.50                        subs     w9, w10, w11, asr #3
Domain: System / Toolchain;